Philips Semiconductors
Product data
DDR PC1600-PC3200 14-bit SSTL_2 registered
driver with differential clock inputs
SSTVF16857
FEATURES
•
Stub-series terminated logic for 2.5 V V
DDQ
(SSTL_2)
•
Optimized for PC 2700 DDR (Double Data Rate) SDRAM
•
Suitable for PC1600/PC2100 DDR SDRAM applications
•
Suitable for PC3200 applications when used at V
DD
= 2.6 V
•
Inputs compatible with JESD8-9 SSTL_2 specifications.
•
Flow-through architecture optimizes PCB layout
•
ESD classification testing is done to JEDEC Standard JESD22.
•
Latch-up testing is done to JEDEC Standard JESD78, which
•
Full DDR300/333/400 solution @ 2.5V when used with PCKV857
•
Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages
•
Superior VREF noise rejection
DESCRIPTION
The SSTVF16857 is a 14-bit SSTL_2 registered driver with
differential clock inputs, designed to operate between 2.3 V and
2.7 V. V
DDQ
must not exceed V
CC
. Inputs are SSTL_2 type with
V
REF
normally at 0.5*V
DDQ
. The outputs support class I which can
be used for standard stub-series applications or capacitive loads.
Master reset (RESET) asynchronously resets all registers to zero.
The SSTVF16857 is intended to be incorporated into standard
DIMM (Dual In-Line Memory Module) designs defined by JEDEC,
such as DDR (Double Data Rate) SDRAM or SDRAM II Memory
Modules. Different from traditional SDRAM, DDR SDRAM transfers
data on both clock edges (rising and falling), thus doubling the peak
bus bandwidth. A DDR DRAM rated at 166 MHz will have a burst
rate of 333 MT/s (mega-transfers per second). The modules require
between 23 and 27 registered control and address lines, so two
14-bit wide devices will be used on each module. The SSTVF16857
is intended to be used for SSTL_2 input and output signals.
The device data inputs consist of differential receivers. One
differential input is tied to the input pin while the other is tied to a
reference input pad, which is shared by all inputs.
The clock input is fully differential to be compatible with DRAM
devices that are installed on the DIMM. However, since the control
inputs to the SDRAM change at only half the data rate, the device
must only change state on the positive transition of the CLK signal.
In order to be able to provide defined outputs from the device even
before a stable clock has been supplied, the device must support an
asynchronous input pin (reset), which when held to the LOW state
will assume that all registers are reset to the LOW state and all
outputs drive a LOW signal as well.
exceeds 100 mA.
Protection exceeds 2000 V to HBM per method A114.
applications
PIN CONFIGURATION
Q1
Q2
GND
V
DDQ
Q3
Q4
Q5
GND
V
DDQ
1
2
3
4
5
6
7
8
9
48 D1
47 D2
46 GND
45 V
CC
44 D3
43 D4
42 D5
41 D6
40 D7
39 CLK-
38 CLK+
37 V
CC
36 GND
35 V
REF
34 RESET
33 D8
32 D9
31 D10
30 D11
29 D12
28 V
CC
27 GND
26 D13
25 D14
SW00685
Q6 10
Q7 11
V
DDQ
12
GND 13
Q8 14
Q9 15
V
DDQ
16
GND 17
Q10 18
Q11 19
Q12 20
V
DDQ
21
GND 22
Q13 23
Q14 24
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
=t
f
v2.5
ns
SYMBOL
t
PHL
/t
PLH
C
I
PARAMETER
Propagation delay; CLK to Qn
Input capacitance
CONDITIONS
C
L
= 30 pF; V
DDQ
= 2.5 V
V
CC
= 2.5 V
TYPICAL
1.9
2.9
UNIT
ns
pF
2003 Sep 19
2
Philips Semiconductors
Product data
DDR PC1600-PC3200 14-bit SSTL_2
registered driver with differential clock inputs
SSTVF16857
BALL CONFIGURATION
1
2
3
4
5
6
A
Q1
NC
NC
NC
NC
D1
B
GND
Q2
V
CC
V
CC
D2
GND
C
Q4
Q3
Q5
D5
D3
D4
D
V
CC
GND
Q6
CLK-
D6
D7
E
V
CC
Q7
CLK+
V
CC
F
GND
Q8
V
REF
GND
G
V
CC
GND
Q9
RESET
D9
D8
H
Q11
Q12
Q10
D10
D12
D11
J
GND
Q13
V
CC
V
CC
D13
GND
K
Q14
NC
NC
NC
NC
D14
SW00952
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Continuous current
4
V
O
= 0 to V
DDQ
V
CC
, V
DDQ
, or GND
V
O
< 0
V
I
< 0
CONDITION
LIMITS
MIN
-0.5
—
-0.5
—
-0.5
—
—
MAX
+4.6
-50
V
DDQ
+ 0.5
-50
V
DDQ
+ 0.5
±50
±100
UNIT
V
mA
V
mA
V
mA
T
stg
Storage temperature range
2
-65
+150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4. The continuous current at V
CC
, V
DDQ
, or GND should not exceed
±100
mA.
2003 Sep 19
4
Philips Semiconductors
Product data
DDR PC1600-PC3200 14-bit SSTL_2
registered driver with differential clock inputs
SSTVF16857
RECOMMENDED OPERATING CONDITIONS
1
SYMBOL
V
CC
V
DDQ
V
REF
V
TT
V
I
V
IH
V
IL
V
IH
V
IL
I
OH
I
OL
PARAMETER
Supply voltage
Output supply voltage
Reference voltage
(V
REF
= 0.5 x V
DDQ
)
Termination voltage
Input voltage
AC HIGH-level input voltage
AC LOW-level input voltage
DC HIGH-level input voltage
DC LOW-level input voltage
HIGH-level output current
LOW-level output current
All inputs
All inputs
All inputs
All inputs
PC1600-PC2700
PC3200
TEST CONDITIONS
MIN
2.3
2.3
1.15
1.25
V
REF
- 40 mV
0
V
REF
+ 310 mV
—
V
REF
+ 150 mV
V
SS
- 0.5 V
—
—
0
TYP
2.5
2.5
1.25
1.30
V
REF
—
—
—
—
—
—
—
—
MAX
2.7
2.7
1.35
1.35
V
REF
+ 40 mV
V
CC
—
V
REF
- 310 mV
V
DDQ
+ 0.5 V
V
REF
- 150 mV
-20
20
70
UNIT
V
V
V
V
V
V
V
V
V
V
mA
mA
°C
T
amb
Operating free-air temperature range
NOTE:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
DC ELECTRICAL CHARACTERISTICS—PC1600-PC2700
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
V
IK
V
OH
V
OL
V
CMR
V
PPmim
PARAMETER
I/O supply voltage
HIGH-level output voltage
LOW-level output voltage
CLK, CLK
CLK, CLK
Data inputs, RESET
I
I
CLK, CLK
V
REF
I
CC
Quiescent supply current
CLK and CLK in opposite
state
1
Data inputs
C
I
CLK, CLK
RESET
TEST CONDITIONS
V
CC
= 2.3 V; I
I
= -18 mA
V
CC
= 2.3 V to 2.7 V; I
OH
= -100
µA
V
CC
= 2.3 V; I
OH
= -16 mA
V
CC
= 2.3 V to 2.7 V; I
OL
= 100
µA
V
CC
= 2.3 V; I
OL
= 16 mA
Common mode range for reliable performance
Minimum peak-to-peak input to ensure logic state
V
CC
= 2.7 V; V
I
= 1.7 V or 0.8 V
V
CC
= 2.7 V; V
I
= 2.7 V or 0 V
V
CC
= 2.7 V; V
I
= 1.7 V or 0.8 V
V
CC
= 2.7 V; V
I
= 2.7 V or 0 V
V
CC
= 2.7 V
V
CC
= 2.7 V; V
I
= 1.7 V or 0.8 V
V
CC
= 2.7 V; V
I
= 2.7 V or 0 V
V
I
= V
REF
±
310 mV,
V
CC
= 2.5 V
V
ICR
= 1.25 V, V
I(PP)
= 360 mV,
V
CC
= 2.5 V
V
I
= V
CC
or GND, V
CC
= 2.5 V
V
REF
= 1.15 V or 1.35 V
V
REF
= 1.15 V or 1.35 V
V
REF
= 1.15 V or 1.35 V
RESET = GND
RESET = V
CC
V
REF
= 1.15 V or 1.35 V
V
REF
= 1.15 V or 1.35 V
V
REF
= 1.15 V or 1.35 V
Temp = 0 to +70
°C
MIN
—
V
CC
- 0.2
1.95
—
—
0.97
—
—
—
—
—
—
—
—
2.5
2.5
2.5
TYP
2
—
—
—
—
—
—
—
0.01
0.01
0.05
0.05
0.05
0.5
10
2.9
2.9
2.9
MAX
-1.2
—
—
0.2
0.35
1.53
360
±5
±5
±5
±5
±5
10
25
3.4
3.4
3.4
pF
V
V
mV
µA
µ
µA
µ
µA
µ
µA
mA
V
UNIT
NOTES:
1. When CLK and CLK are HIGH, typical I
CC
= 25 mA.
2. All typical values are at V
CC
= 2.5 V and T
amb
= 25
°C
(unless otherwise specified).
2003 Sep 19
5
FPGA/CPLD
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