Synchronous DRAM Module, 32MX64, 6ns, CMOS, PDMA144,
HYM72V32M656ALT6-P Parametric
Parameter Name
Attribute value
Maker
SK Hynix
package instruction
DIMM, DIMM144,32
Reach Compliance Code
compliant
Maximum access time
6 ns
Maximum clock frequency (fCLK)
100 MHz
I/O type
COMMON
JESD-30 code
R-PDMA-N144
memory density
2147483648 bit
Memory IC Type
SYNCHRONOUS DRAM MODULE
memory width
64
Number of terminals
144
word count
33554432 words
character code
32000000
Maximum operating temperature
70 °C
Minimum operating temperature
organize
32MX64
Output characteristics
3-STATE
Package body material
PLASTIC/EPOXY
encapsulated code
DIMM
Encapsulate equivalent code
DIMM144,32
Package shape
RECTANGULAR
Package form
MICROELECTRONIC ASSEMBLY
power supply
3.3 V
Certification status
Not Qualified
refresh cycle
8192
Maximum standby current
0.016 A
Maximum slew rate
1.68 mA
Nominal supply voltage (Vsup)
3.3 V
surface mount
NO
technology
CMOS
Temperature level
COMMERCIAL
Terminal form
NO LEAD
Terminal pitch
0.8 mm
Terminal location
DUAL
HYM72V32M656ALT6-P Preview
32Mx64 bits
PC100 SDRAM SODIMM
based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V32M656AT6 Series
DESCRIPTION
The HYM72V32M656AT6 Series are high speed 3.3-Volt Synchronous DRAM Modules composed of eight 16Mx16 bit
Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit EEPROM on a 144-pin Zig Zag Dual pin glass-epoxy
printed circuit board. Three 0.1uF decoupling capacitors per each SDRAM are mounted on the module.
The HYM72V32M656AT6 Series are gold plated socket type Dual In-line Memory Modules suitable for easy interchange
and addition of 256Mbytes
. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths
are internally pipelined to achieve very high bandwidth.
FEATURES
•
•
•
•
PC100 support
144pin SDRAM SO DIMM
Serial Presence Detect with EEPROM
1.25” (31.75mm) Height PCB with double sided com-
ponents
Single 3.3±0.3V power supply
- 1, 2, 4 or 8 or Full page for Sequential Burst
•
•
All device pins are compatible with LVTTL interface
- 1, 2, 4 or 8 for Interleave Burst
Data mask function by DQM
•
Programmable CAS Latency ; 2, 3 Clocks
•
•
•
•
•
•
SDRAM internal banks : four banks
Module bank : two physical bank
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
ORDERING INFORMATION
Part No.
HYM72V32M656AT6-8
HYM72V32M656AT6-P
HYM72V32M656AT6-S
HYM72V32M656ALT6-8
HYM72V32M656ALT6-P
HYM72V32M656ALT6-S
Clock
Frequency
125MHz
100MHz
100MHz
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
Normal
4 Banks
8K
Low Power
TSOP-II
Gold
125MHz
100MHz
100MHz
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 1.2/Feb.01
PC100 SDRAM SODIMM
HYM72V32M656AT6 Series
PIN DESCRIPTION
PIN
CK0, CK1
CKE0
/S0, /S1
BA0, BA1
A0 ~ A12
/RAS, /CAS, /WE
DQM0~DQM7
DQ0 ~ DQ63
VCC
V
SS
SCL
SDA
SA0~2
WP
NC
PIN NAME
Clock Inputs
Clock Enable
Chip Select
SDRAM Bank Address
Address
Row Address Strobe, Column
Address Strobe, Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
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