240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb 1st ver.
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb 1st ver. DDR2 SDRAMs in Fine Ball
Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb 1st ver. based DDR2 Unbuffered DIMM
series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable
for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate 2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
All inputs and outputs are compatible with SSTL_1.8
interface
8 Bank architecture
Posted CAS
Programmable CAS Latency 3, 4, 5
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
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Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 68ball FBGA
133.35 x 30.00 mm form factor
Lead-free products are RoHS compliant
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ORDERING INFORMATION
Part Name
HYMP112U648-E3/C4
HYMP112U728-E3/C4
HYMP125U648-E3/C4
HYMP125U728-E3/C4
HYMP112U64P8-E3/C4
HYMP112U72P8-E3/C4
HYMP125U64P8-E3/C4
HYMP125U72P8-E3/C4
Density
1GB
1GB
2GB
2GB
1GB
1GB
2GB
2GB
Organization
128Mx64
128Mx72
256Mx64
256Mx72
128Mx64
128Mx72
256Mx64
256Mx72
# of
DRAMs
8
9
16
18
8
9
16
18
# of
ranks
1
1
2
2
1
1
2
2
Materials
Leaded
Leaded
Leaded
Leaded
Lead free
Lead free
Lead free
Lead free
ECC
None
ECC
None
ECC
None
ECC
None
ECC
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Apr. 2005
1
1240pin
DDR2 SDRAM Unbuffered DIMMs
Input/Output Functional Description
Symbol
CK[2:0], CK[2:0]
Type
SSTL
Polarity
Differential
Crossing
Active High
Pin Description
CK andk /CK are dirrerential clock inputs. All the DDR2 SDRAM addr/cntl inputs are
sampled on the crossing of positive edge of CK and negative edge of /CK. Output(read)
data is reference to the crossing of CK and /CK (Both directions of crossing)
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the
S[1:0]
RAS, CAS, WE
ODT[1:0]
Vref
V
DDQ
BA[2:0]
SSTL
SSTL
SSTL
Supply
Supply
SSTL
-
Active Low
Active Low
Active High
command decoder when high. When the command decoder is disabled, new com-
mands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1
is selected by S1
/RAS,/CAS and /WE(ALONG WITH S) define the command being entered.
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immu-
nity. For all current DDR2 unbuffered DIMM designs, V
DDQ
shares the same power
plane as V
DD
pins.
Selects which DDR2 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, Address input difines the row
address(RA0~RA15)
During a Read or Write command cycle, Address input defines the column address
when sampled at the cross point of the rising edge of CK and falling edge of CK. In
A[9:0], A10/AP,
A[15:11]
SSTL
-
addition to the column address, AP is used to invoke autoprecharge operation at the
end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-
BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During
a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state
of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre-
DQ[63:0], CB[7:0]
DM[8:0]
SSTL
SSTL
-
Active High
charge.
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled
High coincident with that input data during a write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and
DQS loading.
Power and ground for the DDR2 SDRAM input buffers, and core logic. V
DD
and V
DDQ
pins are tied to V
DD
/V
DDQ
planes on these modules.
Differential
crossing
-
-
-
Supply
Data strobe for input and output data. For Rawcards using x16 organized DRAMs,
DQ0~7 connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin
of the DRAM
These signals are tied at the system planar to either V
SS
or V
DD
to configure the serial
SPD EEPROM.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A
resister must be connected to V
DD
to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from SCL to V
DD
to act as a pull up on the system board.
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power
plane. EEPROM supply is operable from 1.7V to 3.6V.
CKE[1:0]
SSTL
V
DD
,V
SS
Supply
DQS[8:0], DQS[8:0] SSTL
SA[2:0]
SDA
SCL
VDDSPD
Rev. 1.0 / Apr. 2005
3
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