Low Skew, 1-to-4 Differential-to-2.5V,
3.3V LVPECL/ECL Fanout Buffer
Product Discontinuance Notice – Last Time Buy Expires on (1/31/2014)
ICS853S314I
DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS853S314I is a low skew 1-to-4 Differential Fanout Buffer,
designed with clock distribution in mind, accepting two clock
sources into an input MUX. The MUX is controlled by a CLK_SEL
pin. This makes the ICS853S314I very versatile, in that, it can
operate as both a differential clock buffer as well as a signal-
level translator and fanout buffer.
The device is designed on a SiGe process and can operate at
frequencies in excess of 2.7GHz. This ensures negligible jitter
introduction to the timing budget which makes it an ideal choice
for distributing high frequency, high precision clocks across
back planes and boards in communication systems. Internal
temperature compensation guarantees consistent performance
across various platforms.
F
EATURES
•
Four differential ECL/LVPECL level outputs
•
One differential ECL/LVPECL or single-ended input (CLKA)
One differential HSTL or single-ended input (CLKB)
•
Maximum output frequency: 2.7GHz
•
Additive phase jitter, RMS: 0.138ps (typical) @ 156.25MHz,
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 150ps (maximum)
•
LVPECL and HSTL mode operating voltage supply range:
V
CC
= 2.5V±5% or 3.3V±5%, V
EE
= 0V
ECL mode operating voltage supply range:
V
EE
= -3.3V±5% or -2.5V±5%, V
CC
= 0V
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
•
Use replacement part: 8T33FS314
B
LOCK
D
IAGRAM
V
CC
CLKA
nCLKA
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
P
IN
A
SSIGNMENT
V
CC
nc
V
CC
CLK_SEL
CLKA
nCLKA
CLKB
nCLKB
V
EE
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
V
CC
0
V
CC
CLKB
nCLKB
V
EE
1
CLK_SEL
V
EE
ICS853S314I
V
EE
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm body package
F Package
Top View
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm body package
G Package
Top View
ICS853S314AFI REVISION B OCTOBER 4, 2013
1
©2013
Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 3, 10
11, 20
2
4
5
6
7
8
9
12, 13
14, 15
16, 17
Name
V
CC
nc
CLK_SEL
CLKA
nCLKA
CLKB
nCLKB
V
EE
nQ3, Q3
nQ2, Q2
nQ1, Q1
Power
Unused
Input
Input
Input
Input
Input
Power
Output
Output
Output
Type
Description
Positive supply pins.
No connect.
Clock select input. When HIGH, selects CLKB, nCLKB inputs.
Pulldown
When LOW, selects CLKA, nCLKA inputs.
Default non-inver ting differential clock input.
Pulldown
LVPECL/ECL interface levels.
Pullup/
Default inver ting differential clock input. LVPECL/ECL interface levels.
Pulldown
Pulldown Alternative non-inver ting differential clock input. HSTL interface levels.
Pullup/
Alternative inver ting differential clock input. HSTL interface levels.
Pulldown
Negative supply pin.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
18, 19
nQ0, Q0
Output
Differential output pair. LVPECL/ECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
75
75
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. G
ENERAL
S
PECIFICATIONS
Symbol
V
TT
MM
HBM
CDM
LU
Parameter
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Latch-up Immunity
200
4000
2000
200
Test Conditions
Minimum
Typical
V
CC
- 2
Maximum
Units
V
V
V
V
mA
ICS853S314AFI REVISION B OCTOBER 4, 2013
2
©2013
Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Package Thermal Impedance,
θ
JA
20 Lead SSOP
20 Lead TSSOP
Storage Temperature, T
STG
3.9V (LVPECL mode, V
EE
= 0V) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the de-
-3.9V (ECL mode, V
CC
= 0V)
vice. These ratings are stress specifications only. Functional op-
-0.3V to V
CC
+ 0.3 V
eration of product at these conditions or any conditions beyond
0.3V to V
EE
- 0.3V
those listed in the
DC Characteristics
or
AC Characteristics
is
not implied. Exposure to absolute maximum rating conditions
50mA
for extended periods may affect product reliability.
80.8°C/W (0 lfpm)
73.2°C/W (0 lfpm)
-65°C to 150°C
T
ABLE
4A. LVPECL/HSTL DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%
OR
3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
IL
V
IH
I
IN
V
PP
V
CMR
I
IN
Parameter
Input Low Voltage
Input High Voltage
Input Current
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 2
Input Current
V
IN
= V
IL or
V
IN
= V
IH
V
CC
= 3.3V
V
CC
= 2.5V
V
IN
= V
X
± 0.2V
V
CC
-1.2
V
CC
= 3.3V±5%
V
CC
= 2.5V±5%
V
CC
-1.9
V
CC
-1.9
V
CC
-1.005
V
CC
-1.705
V
CC
-1.705
0.4
0.4
0
0.68 - 0.9
V
CC
-1.0
200
V
CC
-0.7
V
CC
-1.5
V
CC
-1.3
V
IN
= V
IL
or V
IN
= V
IH
0.1
1.0
Test Conditions
Minimum
V
CC
-1.810
V
CC
-1.165
Typical
Maximum
V
CC
-1.475
V
CC
-0.880
100
1.3
V
CC
-0.3
100
Units
V
V
µA
V
V
µA
V
V
V
µA
V
V
V
Control Input CLK_SEL
Clock Input Pair CLKA, nCLKA (LVPECL differential signals)
Clock Input Pair CLKB, nCLKB (HSTL differential signals)
V
DIF
V
X
I
IN
V
OH
V
OL
Differential Input Voltage; NOTE 3
Differential Crosspoint Voltage; NOTE 4
Input Current
Output High Voltage
Output Low Voltage
LVPECL Clock Outputs (Q0:Q3, nQ0:nQ3)
Supply Current
Maximum Quiescent Supply Current
I
EE
92
mA
without Output Termination Current
NOTE 1: V
PP
is the minimum differential input voltage swing required to maintain device functionality.
NOTE 2: V
CMR
is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within
the V
CMR
range and the input swing lies within the V
PP
specification.
NOTE 3: V
DIF
is the minimum differential HSTL input voltage swing required for device functionality.
NOTE 4: V
X
is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is
within the V
X
range and the input swing lies within the V
PP
specification.
ICS853S314AFI REVISION B OCTOBER 4, 2013
3
©2013
Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
T
ABLE
4B. ECL DC C
HARACTERISTICS
,
V
CC
= 0V, V
EE
= -2.5V±5%
OR
-3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IL
V
IH
I
IN
V
PP
V
CMR
I
IN
V
OH
V
OL
Parameter
Input Low Voltage
Input High Voltage
Input Current
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 2
Input Current
Output High Voltage
Output Low Voltage
V
EE
= -3.3V±5%
V
EE
= -2.5V±5%
V
IN
= V
IL or
V
IN
= V
IH
-1.2
-1.9
-1.9
-1.005
-1.705
-1.705
V
IN
= V
IL
or V
IN
= V
IH
0.1
V
EE
+ 1.0
Test Conditions
Minimum
-1.810
-1.165
Typical
Maximum
-1.475
-0.880
100
1.3
-0.3
100
-0.7
-1.5
-1.3
Units
V
V
µA
V
V
µA
V
V
V
Control Input CLK_SEL
Clock Input Pair CLKA,/nCLKA (ECL differential signals)
ECL Clock Outputs (Q0:Q3, nQ0:nQ3)
Supply Current
Maximum Quiescent Supply Current
92
mA
I
EE
without Output Termination Current
NOTE 1: V
PP
is the minimum differential input voltage swing required to maintain device functionality.
NOTE 2: V
CMR
is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within
the V
CMR
range and the input swing lies within the V
PP
specification.
ICS853S314AFI REVISION B OCTOBER 4, 2013
4
©2013
Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
T
ABLE
5. AC C
HARACTERISTICS
,
(LVPECL/HSTL): V
CC
= 3.3V±5%
(ECL): V
EE
= -3.3V±5%
Symbol Parameter
V
PP
V
CMR
f
CLK
t
PD
V
DIF
V
X
V
O
(pp)
Differential Input Voltage; NOTE 1
Differential Input Crosspoint Voltage;
NOTE 2
Input Frequency; NOTE 3
Propagation Delay, CLKA or CLKB to
Output Pair
HSTL Differential Input Voltage; NOTE 4
HSTL Input Differential Crosspoint
Voltage; NOTE 5
Differential Output Voltage
(peak-to-peak)
Output Skew
Par t-to-Par t Skew; NOTE 6
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Output Pulse Skew; NOTE 7
OR
OR
2.5V±5%, V
EE
= 0V,
OR
-2.5V±5%, V
CC
= 0V; T
A
= -40°C
TO
85°C
Minimum
0.15
V
EE
+ 1.0
Typical
Maximum
1.3
V
CC
- 0.3
2.7
280
0.4
V
EE
+ 0.01
f
O
< 300MHz
f
O
< 1.5GHz
0.45
0.3
0.72
0.55
650
1.0
V
CC
- 1.0
0.95
0.95
50
150
Units
V
V
GHz
ps
V
V
V
V
ps
ps
ps
ps
75
ps
Test Conditions
t
sk(o)
t
sk(pp)
tjit
t
sk(p)
156.25MHz @ 3.3V,
(1.875MHz - 20MHz)
312.5MHz @ 3.3V,
(1.875MHz - 20MHz)
660MHz
0.138
0.092
Output Rise/Fall Time
20% to 80%
0.05
0.3
ns
t
R
/ t
F
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
AC characteristics apply for parallel output termination of 50
Ω
to V
TT
.
NOTE 1: V
PP
is the minimum differential ECL/LVPECL input voltage swing required to maintain AC characteristics including
t
PD
and device-to-device skew.
NOTE 2: V
CMR
is the crosspoint of the differential ECL/LVPECL input signal. Normal AC operation is obtained when the
crosspoint is within the V
CMR
range and the input swing lies within the V
PP
specificatiion. Violation of V
CMR
or V
PP
impacts the
device propagation delay, device and par t-to-par t skew.
NOTE 3: The ICS853S314I is fully operational up to 2.7GHz and is characterized up to 1.5GHz.
NOTE 4:V
DIF
is the minimum differential HSTL input voltage swing required to maintain AC characteristics including t
PD
and
device-to-device skew.
NOTE 5: V
X
is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is
within the V
X
range and the input swing lies within the V
DIF
specification. Violation of V
X
or V
DIF
impacts the device
propgation delay, device and par t-to-par t skew.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7: Output pulse skew is the absolute value of the difference of the propagation delay times:
⎪
t
PLH
- t
PHL
⎪.
ICS853S314AFI REVISION B OCTOBER 4, 2013
5
©2013
Integrated Device Technology, Inc.
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