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70P3599S166DRG

Description
Dual-Port SRAM, 128KX36, 12ns, PQFP208, 28 X 28 MM, 4.10 MM HEIGHT, PQFP-208
Categorystorage    storage   
File Size315KB,28 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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70P3599S166DRG Overview

Dual-Port SRAM, 128KX36, 12ns, PQFP208, 28 X 28 MM, 4.10 MM HEIGHT, PQFP-208

70P3599S166DRG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionFQFP,
Contacts208
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time12 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 codeS-PQFP-G208
JESD-609 codee3
length28 mm
memory density4718592 bit
Memory IC TypeDUAL-PORT SRAM
memory width36
Humidity sensitivity level3
Number of functions1
Number of terminals208
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX36
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Package shapeSQUARE
Package formFLATPACK, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height4.1 mm
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width28 mm
Features:
HIGH-SPEED 1.8V
PRELIMINARY
256/128K x 36
IDT70P3519/99
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V/2.5V/1.8V INTERFACE
True Dual-Port memory cells which allow simultaneous
access of the same memory location
Low Power
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)
– Industrial: 3.6ns (166MHz)
Selectable Pipelined or Flow-Through output mode
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Counter enable and repeat features
Interrupt and Collision Detection Flags
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
1.8V (±100mV) power supply for core
LVTTL compatible,1.8V to 3.3V power supply for I/Os and
control signals on each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz
Available in a 256-pin Ball Grid Array (BGA), a 208-pin
Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball
Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Due to limited pin count JTAG is not supported on the 208-
pin PQFP package
Green parts available, see ordering information
Functional Block Diagram
BE
3L
BE
2L
BE
1L
BE
0L
BE
3R
BE
2R
BE
1R
BE
0R
FT/PIPE
L
1/0
0a 1a
a
0b 1b
b
0c 1c
c
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
a
1/0
FT/PIPE
R
R/W
L
R/W
R
CE
0L
CE
1L
1
0
1/0
B B
WW
0 1
L L
B B B B
WWWW
2 3 3 2
L L R R
B B
WW
1 0
R R
1
0
1/0
CE
0R
CE
1R
OE
L
OE
R
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
1d 0d 1c 0c 1b 0b 1a 0a
0a 1a 0b 1b 0c 1c 0d 1d
0/1
,
FT/PIPE
R
FT/PIPE
L
0/1
a bc d
dcba
256/128K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35 L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
17L(1)
A
0L
REPEAT
L
ADS
L
CNTEN
L
A
17R(
1)
CLK
R
,
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
REPEAT
R
ADS
R
CNTEN
R
TDI
TCK
T MS
T RST
CE
0 L
CE1L
R /
W
L
INTERRUPT
COLLISION
DETECTION
LOGIC
CE
0 R
CE1 R
R/
W
R
JTAG
TDO
COL
R
INT
R
COL
L
INT
L
ZZ
L
(2)
NOTES:
1. Address A
17
is a NC for the IDT70P3599.
+. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
ZZ
CONTROL
LOGIC
ZZ
R
(2)
7144 drw 01
JANUARY 2009
DSC 7144/2
1
©2009 Integrated Device Technology, Inc.

70P3599S166DRG Related Products

70P3599S166DRG 70P3519S166DRG
Description Dual-Port SRAM, 128KX36, 12ns, PQFP208, 28 X 28 MM, 4.10 MM HEIGHT, PQFP-208 Dual-Port SRAM, 256KX36, 12ns, PQFP208, 28 X 28 MM, 4.10 MM HEIGHT, PQFP-208
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code QFP QFP
package instruction FQFP, FQFP,
Contacts 208 208
Reach Compliance Code compliant compliant
ECCN code 3A991.B.2.A 3A991.B.2.A
Maximum access time 12 ns 12 ns
Other features FLOW-THROUGH OR PIPELINED ARCHITECTURE FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code S-PQFP-G208 S-PQFP-G208
JESD-609 code e3 e3
length 28 mm 28 mm
memory density 4718592 bit 9437184 bit
Memory IC Type DUAL-PORT SRAM DUAL-PORT SRAM
memory width 36 36
Humidity sensitivity level 3 3
Number of functions 1 1
Number of terminals 208 208
word count 131072 words 262144 words
character code 128000 256000
Operating mode SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 70 °C 70 °C
organize 128KX36 256KX36
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code FQFP FQFP
Package shape SQUARE SQUARE
Package form FLATPACK, FINE PITCH FLATPACK, FINE PITCH
Parallel/Serial PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) 260 260
Certification status Not Qualified Not Qualified
Maximum seat height 4.1 mm 4.1 mm
Maximum supply voltage (Vsup) 1.9 V 1.9 V
Minimum supply voltage (Vsup) 1.7 V 1.7 V
Nominal supply voltage (Vsup) 1.8 V 1.8 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn)
Terminal form GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature 30 30
width 28 mm 28 mm

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