PCI EXPRESS™ JITTER ATTENUATOR
ICS874003-02
G
ENERAL
D
ESCRIPTION
The ICS874003-02 is a high performance Dif-
ferential-to-LVDS Jitter Attenuator designed for
HiPerClockS™
use in PCI Express systems. In some PCI Express
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a jitter attenuator may be required to attenuate
high frequency random and deterministic jitter components
from the PLL synthesizer and from the system board. The
ICS874003-02 has a bandwidth of 400kHz. The 400kHz
provides an intermediate bandwidth that can easily track
tr iangular spread profiles, while providing good jitter
attenuation.
F
EATURES
•
Three Differential LVDS output pairs
•
One Differential clock input
•
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency range: 98MHz - 320MHz
•
Input frequency range: 98MHz - 128MHz
•
VCO range: 490MHz - 640MHz
•
Cycle-to-cycle jitter: 35ps (maximum)
•
Supports PCI-Express Spread-Spectrum Clocking
•
The 400kHz bandwidth mode allows the system designer to
make jitter attenuation/tracking skew design trade-offs
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
The ICS874003-02 uses IDT’s 3 Generation FemtoClock
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
rd
TM
F_SEL[2:0] F
UNCTION
T
ABLE
F_SEL2
0
1
0
1
0
1
Inputs
F_SEL1
0
0
1
1
0
0
1
1
F_SEL0
0
0
0
0
1
1
1
1
Outputs
QA0/nQA0, QA0/nQA0
÷2
÷5
÷4
÷2
÷2
÷5
÷4
÷4
QB0/nQB0
÷2
÷2
÷2
÷4
÷5
÷4
÷5
÷4
B
LOCK
D
IAGRAM
OEA Pullup
F_SEL2:0
Pulldown
3
0
1
P
IN
A
SSIGNMENT
QA0
÷5
÷4
÷2
(default)
CLK Pulldown
nCLK
Pullup
nQA0
QA1
Phase
Detector
VCO
490 - 640MHz
3
nQA1
QA1
V
DDO
QA0
nQA0
MR
F_SEL0
nc
V
DDA
F_SEL1
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nQA1
V
DDO
QB0
nQB0
F_SEL2
OEB
GND
nCLK
CLK
OEA
M = ÷5
(fixed)
÷5
÷4
÷2
(default)
QB0
ICS874003-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
nQB0
MR Pulldown
Pullup
OEB
G Package
Top View
1
ICS874003AG-02 REV A March 3, 2009
IDT
™
/ ICS
™
PCI EXPRESS™ JITTER ATTENUATOR
ICS874003-02
PCI EXPRESS™ JITTER ATTENUATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 20
2, 19
3, 4
5
6,
9,
16
7
8
10
11
12
13
14
15
17, 18
Name
QA1, nQA1
V
DDO
QA0, nQA0
MR
F_SEL0,
F_SEL1,
F_SEL2
nc
V
DDA
V
DD
OEA
CLK
nCLK
GN D
OEB
nQB0, QB0
Power
Output
Input
Type
Output
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (nQx) to go low and the inver ted outputs
Pulldown
(Qx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
Pulldown
Frequency select pin for QAx/nQAx and QBx0/nQB0 outputs.
LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
Pullup
active. When LOW, the QAx/nQAx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Power supply ground.
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
active. When LOW, the QBx/nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Input
Unused
Power
Power
Input
Input
Input
Power
Input
Output
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Inputs
OEA
0
1
OEB
0
1
HiZ
Enabled
Outputs
QA0/nQA0, QA1/nQA1
QB0/nQB0
HiZ
Enabled
IDT
™
/ ICS
™
PCI EXPRESS™ JITTER ATTENUATOR
2
ICS874003AG-02 REV A March 3, 2009
ICS874003-02
PCI EXPRESS™ JITTER ATTENUATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
73.2°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.12
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
75
12
75
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
OEA, OEB
F_SEL0, F_SEL1
F_SEL2, MR
OEA, OEB
F_SEL0, F_SEL1
F_SEL2, MR
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
I
IL
Input Low Current
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
-150
0.15
1.3
V
V
5
150
µA
Minimum
Typical
Maximum
150
Units
µA
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
V
DD
- 0.85
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK and FB_IN, nFB_IN is V
DD
+ 0.3V.
IDT
™
/ ICS
™
PCI EXPRESS™ JITTER ATTENUATOR
3
ICS874003AG-02 REV A March 3, 2009
ICS874003-02
PCI EXPRESS™ JITTER ATTENUATOR
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
∆
V
OD
V
OS
∆
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.2
1.35
Test Conditions
Minimum
275
Typical
375
Maximum
485
50
1.5
50
Units
mV
mV
V
mV
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
Parameter
Output Frequency
Cycle-to-Cycle Jitter, NOTE 1
Output Skew; NOTE 2, 3
Bank Skew; NOTE 1, 4
Output Rise/Fall Time
Bank A
20% to 80%
275
Test Conditions
Minimum
98
Typical
Maximum
320
35
145
55
72 5
53
Units
MHz
ps
ps
ps
ps
%
t
jit(cc)
t
sk(o)
t
sk(b)
t
R
/ t
F
o dc
Output Duty Cycle
47
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
IDT
™
/ ICS
™
PCI EXPRESS™ JITTER ATTENUATOR
4
ICS874003AG-02 REV A March 3, 2009
ICS874003-02
PCI EXPRESS™ JITTER ATTENUATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
DD
SCOPE
3.3V±5%
POWER SUPPLY
+ Float GND –
V
DD,
V
DDO
Qx
V
DDA
nCLK
V
PP
LVDS
nQx
Cross Points
V
CMR
CLK
GND
3.3V LVDS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
nQA0, nQA1,
nQB0
QA0, QA1,
QB0
nQx
Qx
t
cycle n
➤
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
C
YCLE
-
TO
-C
YCLE
J
ITTER
nQXx
QXx
nQXy
QXy
nQA0, nQA1,
nQB0
QA0, QA1,
QB0
t
sk(b)
Where X = A or B
B
ANK
S
KEW
IDT
™
/ ICS
™
PCI EXPRESS™ JITTER ATTENUATOR
➤
➤
t
cycle n+1
➤
nQy
Qy
t
sk(o)
O
UTPUT
S
KEW
t
PW
t
PERIOD
odc =
t
PW
t
PERIOD
x 100%
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
5
ICS874003AG-02 REV A March 3, 2009
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