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IDT70V9089L12PFGI

Description
Dual-Port SRAM, 64KX8, 25ns, CMOS, PQFP100, TQFP-100
Categorystorage    storage   
File Size197KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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IDT70V9089L12PFGI Overview

Dual-Port SRAM, 64KX8, 25ns, CMOS, PQFP100, TQFP-100

IDT70V9089L12PFGI Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionLFQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time25 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 codeS-PQFP-G100
JESD-609 codee3
length14 mm
memory density524288 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count65536 words
character code64000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize64KX8
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm

IDT70V9089L12PFGI Preview

HIGH-SPEED 3.3V 64K x 8
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features:
x
x
PRELIMINARY
IDT70V9089S/L
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 9/12/15ns (max.)
Low-power operation
– IDT70V9089S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V9089L
Active: 429mW (typ.)
Standby: 660mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pin
Counter enable and reset features
x
x
x
x
x
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66MHz operation in the Pipelined output mode
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100 pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/
W
L
OE
L
R/
W
R
OE
R
1
0
0/1
CE
0L
CE
1L
1
0
0/1
CE
0R
CE
1R
FT
/PIPE
L
I/O
0L
- I/O
7L
0/1
1
0
0
1
0/1
FT
/PIPE
R
I/O
0R
- I/O
7R
I/O
Control
I/O
Control
A
15L
A
0L
CLK
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
15R
A
0R
CLK
R
ADS
L
CNTEN
L
CNTRST
L
ADS
R
CNTEN
R
CNTRST
R
3750 drw 01
MARCH 2000
1
©2000 Integrated Device Technology, Inc.
DSC 3750/6
IDT70V9089S/L
High Speed 3.3V 64K x 8 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Description:
The IDT70V9089 is a high-speed 64K x 8 bit synNchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times.
With an input data register, the IDT70V9089 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by
CE
0
and CE
1,
permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 429mW of power.
Pin Configurations
(1,2,3)
CNTEN
L
ADS
L
CLK
R
Index
CLK
L
CNTEN
R
GND
ADS
R
NC
NC
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
NC
V
CC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
NC
NC
NC
NC
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
IDT70V9089PF
PN100-1
(4)
100-PIN TQFP
TOP VIEW
(5)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
NC
NC
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
NC
GND
NC
NC
NC
NC
CE
0L
CE
1L
CE
0R
CE
1R
CNTRST
L
R/
W
L
OE
L
FT
/PIPE
L
NC
NC
CNTRST
R
R/
W
R
OE
R
FT
/PIPE
R
GND
NC
3750 drw 02
,
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
GND
NC
I/O
7
L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
IL
I/O
0L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
NC
NC
NC
2
6.42
IDT70V9089S/L
High Speed 3.3V 64K x 8 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
Ground
3750 tbl 01
CE
0L
, CE
1L
R/
W
L
CE
0R
, CE
1R
R/
W
R
OE
L
A
0L
- A
15L
I/O
0L
- I/O
7L
CLK
L
OE
R
A
0R
- A
15R
I/O
0R
- I/O
7R
CLK
R
ADS
L
CNTEN
L
CNTRST
L
FT
/PIPE
L
ADS
R
CNTEN
R
CNTRST
R
FT
/PIPE
R
V
CC
GND
Truth Table I—Read/Write and
Enable Control
(1,2,3)
OE
X
X
X
L
H
CLK
X
CE
0
H
X
L
L
L
CE
1
X
L
H
H
H
R/
W
X
X
L
H
X
I/O
0-7
High-Z
High-Z
D
IN
D
OUT
High-Z
Mode
Deselected
Deselected
Write
Read
Outputs Disabled
3750 tbl 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signal.
Truth Table II—Address Counter Control
(1,2)
Address
X
An
X
X
Previous
Address
X
X
An
An
CLK
ADS
H
L
(4)
H
H
CNTEN
H
H
H
L
(5)
CNTRST
L
H
H
H
I/O
(3)
D
I/O
(0)
D
I/O
(n)
D
I/O
(n)
D
I/O
(n+1)
Mode
Counter Reset to Address 0
External Address Utilized
External Address Blocked—Counter Disabled
Counter Enable—Internal Address Generation
3750 tbl 03
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
and
OE
= V
IL
; CE
1
and R/W = V
IH
.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
is independent of all other signals including
CE
0
and CE
1
.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
and CE
1
.
6.42
3
IDT70V9089S/L
High Speed 3.3V 64K x 8 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
(1,2)
Grade
Commercial
Industrial
Ambient
Temperature
0
O
C to +70
O
C
-40 C to +85 C
O
O
Recommended DC Operating
Conditions
Symbol
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.2
-0.3
(2)
Typ.
3.3
0
____
Max.
3.6
0
V
CC
+ 0.3V
(1)
0.8
Unit
V
V
V
V
3750 tbl 05
GND
0V
0V
Vcc
3.3V
+
0.3V
3.3V
+
0.3V
3750 tbl 04
V
CC
GND
V
IH
V
IL
NOTES:
1. This is the parameter T
A
.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
____
NOTES:
1. V
TERM
must not exceed V
CC
+0.3V.
2. V
IL
> -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +4.6
Unit
V
Capacitance
(T
A
= +25°C, f = 1.0MH
z
)
Symbol
C
IN
C
OUT
(3)
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
3750 tbl 07
T
BIAS
T
STG
I
OUT
-55 to +125
-55 to +125
50
o
C
C
o
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
mA
3750 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
cc
+ 0.3V.
4
6.42
IDT70V9089S/L
High Speed 3.3V 64K x 8 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V ± 0.3V)
70V9089S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 3.3V, V
IN
= 0V to V
CC
Min.
___
70V9089L
Min.
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3750 tbl 08
CE
0
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
___
___
___
___
2.4
2.4
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(6,7)
(V
CC
= 3.3V ± 0.3V)
70V9089X9
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Test Condition
Version
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
(4)
180
180
____
____
70V9089X12
Com'l Only
Typ.
(4)
150
150
____
____
70V9089X15
Com'l Only
Typ.
(4)
130
130
____
____
Max.
260
225
____
____
Max.
240
205
____
____
Max.
220
185
____
____
Unit
mA
CE
L
and
CE
R
= V
IL
Outputs Open
f = f
MAX
(1)
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and
CE
R
= V
IH
f = f
MAX
(1)
50
50
____
____
75
65
____
____
40
40
____
____
65
50
____
____
30
30
____
____
55
35
____
____
mA
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(3)
COM'L
IND
COM'L
IND
COM'L
IND
110
110
____
____
170
150
____
____
100
100
____
____
160
140
____
____
90
90
____
____
150
130
____
____
mA
Active Port Outputs Open,
f=f
MAX
(1)
Both Ports
CE
R
and
CE
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
1.0
0.4
____
____
5
3
____
____
1.0
0.4
____
____
5
3
____
____
1.0
0.4
____
____
5
3
____
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, Active Port
Outputs Open, f = f
MAX
(1)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
100
100
____
____
160
140
____
____
90
90
____
____
150
130
____
____
80
80
____
____
140
120
____
____
mA
NOTES:
1. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CYC
, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 3.3V, TA = 25°C for Typ, and are not production tested. I
CC DC
(f=0) = 90mA (Typ).
5.
CE
X
= V
IL
means
CE
0X
= V
IL
and CE
1X
= V
IH
CE
X
= V
IH
means
CE
0X
= V
IH
or CE
1X
= V
IL
CE
X
< 0.2V means
CE
0X
< 0.2V and CE
1X
> V
CC
- 0.2V
CE
X
> V
CC
- 0.2V means
CE
0X
> V
CC
- 0.2V or CE
1X
< 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
3750 tbl 09
6.42
5

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