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Datasheet> All Categories > logic> logic> 74LVC374PWDH-T
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74LVC374PWDH-T

Description
LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
Categorylogic    logic   
File Size128KB，10 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Download Datasheet Parametric View All

74LVC374PWDH-T Overview

LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20

74LVC374PWDH-T Parametric

Parameter NameAttribute value
MakerNXP
package instructionTSSOP,
Reach Compliance Codeunknown
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-G20
length6.5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)8.5 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)1.2 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width4.4 mm

74LVC374PWDH-T Preview

INTEGRATED CIRCUITS
74LVC374
Octal D-type flip-flop;
positive edge-trigger (3-State)
Product specification
Supersedes data of February 1996
IC24 Data Handbook
1997 Mar 12
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LVC374
FEATURES
•
Wide supply voltage range of 1.2V to 3.6V
•
In accordance with JEDEC standard no. 8-1A
•
Inputs accept voltages up to 5.5V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
8-bit positive edge-triggered register
•
Independent register and 3-State buffer operation
•
Output drive capability 50W transmission lines @ 85°C
DESCRIPTION
The 74LVC374 is a high-performance low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families. Inputs can be driven from either 3.3V or 5V
devices. This feature allows the use of these devices as translators
in a mixed 3.3V/5V environment.
The 74LV374 is an octal D-type flip-flop featuring separate D-type
inputs for each flip-flop and 3-State outputs for bus oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition.
When OE is LOW, the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops. The ‘374’ is functionally identical to the ‘574’
but the ‘574’ has a different pin arrangement.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
v2.5
ns
SYMBOL
t
PHL
/t
PLH
f
max
C
I
C
PD
PARAMETER
Propagation delay
CP to Qn
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip-flop
Notes 1 and 2
CONDITIONS
C
L
= 50pF
V
CC
= 3.3V
C
L
= 50pF
V
CC
= 3.3V
TYPICAL
4.8
150
5.0
28
UNIT
ns
MHz
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
)Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
20-Pin Plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC374 D
74LVC374 DB
74LVC374 PW
NORTH AMERICA
74LVC374 D
74LVC374 DB
74LVC374PW DH
PKG. DWG. #
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
PIN DESCRIPTION
PIN
NUMBER
1
2, 5, 6, 9,
12, 15, 16, 19
3, 4, 7, 8,
13, 14, 17, 18
10
11
20
SV00338
SYMBOL
OE
Q0 to Q7
D0 to D7
GND
CP
V
CC
FUNCTION
Output enable input (active-LOW)
3-State flip-flop outputs
Data inputs
Ground (0V)
Clock input
(LOW-to-HIGH, edge-triggered)
Positive supply voltage
GND 10
1997 Mar 12
2
853–1942 17843
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LVC374
LOGIC SYMBOL
11
FUNCTIONAL DIAGRAM
3
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
13
14
17
18
11
1
4
7
8
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
OE
Q
0
Q
1
Q
2
Q
3
3-STATE
OUTPUTS
Q
4
Q
5
Q
6
Q
7
2
5
6
9
12
15
16
19
FF1
to
FF8
SV00339
1
LOGIC SYMBOL (IEEE/IEC)
11
1
C1
EN1
SV00341
FUNCTION TABLE
OPERATING
MODES
2
INPUTS
OE
L
L
H
H
CP
↑
↑
↑
↑
Dn
l
h
l
h
INTERNAL
FLIP-FLOPS
L
H
L
H
OUTPUTS
Q0 to Q7
L
H
Z
Z
3
1D
Load and
read register
Load register
and disable
outputs
4
7
8
13
14
17
18
5
6
9
12
15
16
19
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
Z = High impedance OFF-state
↑
= LOW–to–HIGH clock transition
SV00340
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SV00342
1997 Mar 12
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LVC374
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
CC
V
I
V
I/O
V
O
T
amb
t
r
, t
f
PARAMETER
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
DC input voltage range for I/Os
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
CONDITIONS
MIN
2.7
1.2
0
0
0
–40
0
0
MAX
3.6
3.6
5.5
V
CC
V
CC
+85
20
10
V
V
V
V
V
°C
ns/V
UNIT
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
V
CC
I
IK
V
I
V
I/O
I
OK
V
OUT
I
OUT
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
DC input voltage range for I/Os
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
O
uV
CC
or V
O
t
0
Note 2
V
O
= 0 to V
CC
V
I
t0
Note 2
CONDITIONS
RATING
–0.5 to +6.5
–50
–0.5 to +5.5
–0.5 to V
CC
+0.5
"50
–0.5 to V
CC
+0.5
"50
"100
–60 to +150
500
500
UNIT
V
mA
V
V
mA
V
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1997 Mar 12
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LVC374
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
V
IH
HIGH level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
LOW level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
O
OH
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= –100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –12mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –24mA
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
OL
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
I
I
I
IHZ
/I
ILZ
I
OZ
I
CC
∆I
CC
Input leakage current
Input current for common I/O pins
3-State output OFF-state current
Quiescent supply current
Additional quiescent supply current per
input pin
V
CC
= 3 6V; V
I
= 5 5V or GND
3.6V;
5.5V
V
CC
= 3.6V; V
I
= V
CC
or GND
V
CC
= 3.6V; V
I
= V
IH
or V
IL
; V
O
= V
CC
or GND
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
V
CC
= 2.7V to 3.6V; V
I
= V
CC
–0.6V; I
O
= 0
Not for I/O pins
"0.1
"0
1
"0.1
0.1
0.1
5
GND
V
CC
*0.5
V
CC
*0.2
V
CC
*0.6
V
CC
*1.0
0.40
0.20
0.55
"5
"15
"10
20
500
µA
µA
µA
µA
µA
V
V
CC
V
V
CC
2.0
GND
V
0.8
TYP
1
MAX
V
UNIT
V
IL
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
v
2.5 ns; C
L
= 50 pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
±0.3V
MIN
t
PHL
/t
PLH
t
PZH
/t
PZL
t
PHZ
/t
PLZ
t
W
t
su
t
h
f
max
Propagation delay
CP to Qn
3-State output enable time
OE to Qn
3-State output disable time
OE to Qn
Clock pulse width HIGH or
LOW
Set-up time
Dn to CP
Hold time
Dn to CP
Maximum clock pulse
frequency
Figures 1, 4
Figures 2, 4
Figures 2, 4
Figure 1
Figure 3
Figure 3
Figure 1
1.5
1.5
1.5
–
–
1.0
75
TYP
1
4.8
4.0
3.5
3.0
0.4
–0.4
150
MAX
8.5
7.5
6.0
–
–
–
1.0
V
CC
= 2.7V
MIN
1.5
1.5
1.5
MAX
9.5
8.0
6.5
–
–
–
V
CC
= 1.2V
TYP
21
17
8.0
–
–
–
ns
ns
ns
ns
ns
ns
MHz
UNIT
NOTE:
1. These typical values are at V
CC
= 3.3V and T
amb
= 25°C.
1997 Mar 12
5
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