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IDT72230L50TC

Description
FIFO, 2KX8, 25ns, Synchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, THIN, CERAMIC, DIP-28
Categorystorage    storage   
File Size164KB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT72230L50TC Overview

FIFO, 2KX8, 25ns, Synchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, THIN, CERAMIC, DIP-28

IDT72230L50TC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeDIP
package instruction0.300 INCH, SIDE BRAZED, THIN, CERAMIC, DIP-28
Contacts28
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time25 ns
Maximum clock frequency (fCLK)20 MHz
period time50 ns
JESD-30 codeR-CDIP-T28
JESD-609 codee0
length35.56 mm
memory density16384 bit
Memory IC TypeOTHER FIFO
memory width8
Number of functions1
Number of terminals28
word count2048 words
character code2000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize2KX8
Output characteristics3-STATE
ExportableYES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP28,.3
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum standby current0.16 A
Maximum slew rate0.16 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
CMOS SyncFIFO™
64 x 8, 256 x 8, 512 x 8,
1024 x 8, 2048 x 8 and 4096 x 8
Integrated Device Technology, Inc.
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
FEATURES:
64 x 8-bit organization (IDT72420)
256 x 8-bit organization (IDT72200)
512 x 8-bit organization (IDT72210)
1024 x 8-bit organization (IDT72220)
2048 x 8-bit organization (IDT72230)
4096 x 8-bit organization (IDT72240)
12 ns read/write cycle time (IDT72420/72200/72210)
15 ns read/write cycle time (IDT72220/72230/72240)
Read and write clocks can be asynchronous or
coincidental
Dual-Ported zero fall-through time architecture
Empty and Full flags signal FIFO status
Almost-empty and almost-full flags set to Empty+7 and
Full-7, respectively
Output enable puts output data bus in high-impedance
state
Produced with advanced submicron CMOS technology
Available in 28-pin 300 mil plastic DIP and 300 mil
ceramic DIP
For surface mount product please see the IDT72421/
72201/72211/72221/72231/72241 data sheet
Military product compliant to MIL-STD-883, Class B
Industrial temperature range (-40
O
C to +85
O
C) is
available, tested to military electrical specifications
DESCRIPTION:
The IDT72420/72200/72210/72220/72230/72240
SyncFIFO™ are very high-speed, low-power First-In, First-
Out (FIFO) memories with clocked read and write controls.
The IDT72420/72200/72210/72220/72230/72240 have a 64,
256, 512, 1024, 2048, and 4096 x 8-bit memory array, respec-
tively. These FIFOs are applicable for a wide variety of data
buffering needs, such as graphics, Local Area Networks
(LANs), and interprocessor communication.
These FIFOs have 8-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and a write
enable pin (WEN). Data is written into the Synchronous FIFO
on every clock when WEN is asserted. The output port is
controlled by another clock pin (RCLK) and a read enable pin
(REN). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
These Synchronous FIFOs have two end-point flags, Empty
(EF) and Full (FF). Two partial flags, Almost-Empty (AE) and
Almost-Full (AF), are provided for improved system control.
The partial ( AE) flags are set to Empty+7 and Full-7 for AE and
AF respectively.
The IDT72420/72200/72210/72220/72230/72240 are fabri-
cated using IDT’s high-speed submicron CMOS technology.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0 - D7
WEN
INPUT REGISTER
FLAG
LOGIC
RAM ARRAY
64 x 8
256 x 8
512 x 8
WRITE CONTROL
LOGIC
EF
AE
AF
FF
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
RS
OE
Q0 - Q7
REN
2680 drw 01
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
NOVEMBER 1996
DSC-2680/6
5.12
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