K7A403600M
Document Title
128Kx36-Bit Synchronous Pipelined Burst SRAM
128Kx36 Synchronous SRAM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
History
Initial draft
Change 7.5 bin to 7.2
Change speed symbol 6.0/6.7/7.2/8.5 to 60/67/72/85
Draft Date
May . 15. 1997
January . 13 . 1998
February. 02. 1998
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Change DC characteristics V
DD
condition from V
DD
=3.3V+10%/-5% Change February. 12. 1998
Input/output leackage currant for
±1µA
to
±2µA
Modify Read timing & Power down cycle timing.
Change I
SB2
value from 30mA to 20mA.
Remove DC characteristics I
SB1
- L ver.& I
SB2
- L ver .
Remove Low power version.
Add 119BGA(7x17 Ball Grid Array Package)
Change Undershoot spec
from -3.0V(pulse width
≤
20ns) to -2.0V(pulse width
≤
t
CYC
/2)
Add Overshoot spec 4.6V((pulse width
≤
t
CYC
/2)
Change V
IH
max from 5.5V to V
DD
+0.5V
March. 11 . 1998
0.4
Preliminary
0.5
April. 14. 1998
Preliminary
0.6
May.13. 1998
Change I
SB2
value from 20mA to 30mA.
Change V
DD
condition from V
DD
=3.3V+10%/-5% to V
DD
=3.3V+0.3V/-0.165V.
Modify DC characteristics( Input Leakage Current test Conditions)
form V
DD
=V
SS to
V
DD
to Max.
Final spec Release
Add V
DDQ
Supply voltage( 2.5V )
Remove 119BGA(7x17 Ball Grid Array Package) .
May.14.1998
Preliminary
0.7
Preliminary
1.0
2.0
3.0
May. 15. 1998
Dec. 02. 1998
Nov. 26. 1999
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
November 1999
Rev 3.0
K7A403600M
128Kx36 Synchronous SRAM
128Kx36-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V+0.3V/-0.165V Power Supply.
• V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A Package .
GENERAL DESCRIPTION
The K7A403600M is a 4,718,592-bit Synchronous Static Ran-
dom Access Memory designed for high performance second
level cache of Pentium and Power PC based System.
It is organized as 128K words of 36bits and integrates address
and control registers, a 2-bit burst address counter and added
some new functions for high performance cache RAM applica-
tions; GW, BW, LBO, ZZ. Write cycles are internally self-timed
and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7A403600M is fabricated using SAMSUNG′s high perfor-
mance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -16 -15 -14 -11 Unit
t
CYC
t
CD
t
OE
6.0 6.7 7.2 8.5
3.5 3.8 4.0 4.0
3.5 3.8 4.0 4.0
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A
0
~A
1
A
0
~A
16
ADDRESS
REGISTER
A
2
~A
16
A′
0
~A′
1
128Kx36
MEMORY
ARRAY
ADSP
CS
1
CS
2
CS
2
GW
BW
WEa
WEb
WEc
WEd
OE
ZZ
DQa
0
~ DQd
7
DQPa ~ DQPd
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
-2-
November 1999
Rev 3.0
K7A403600M
PIN CONFIGURATION
(TOP VIEW)
128Kx36 Synchronous SRAM
ADSC
ADSP
WEd
WEb
WEa
WEc
ADV
83
CLK
CS
1
CS
2
CS
2
V
DD
GW
V
SS
BW
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
11
A
12
A
13
A
14
A
15
LBO
N.C.
N.C.
V
SS
N.C.
PIN NAME
SYMBOL
A
0
- A
16
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
V
DDQ
V
SSQ
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
TQFP PIN NO.
15,41,65,91
17,40,67,90
14,16,38,39,42,43,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
32,33,34,35,36,37,
44,45,46,47,48,49,
50,81,82,99,100
ADV
Burst Address Advance
83
ADSP
Address Status Processor 84
ADSC
Address Status Controller 85
CLK
Clock
89
CS
1
Chip Select
98
CS
2
Chip Select
97
CS
2
Chip Select
92
WEx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
Output Enable
86
GW
Global Write Enable
88
BW
Byte Write Enable
87
ZZ
Power Down Input
64
LBO
Burst Mode Control
31
N.C.
Output Power Supply
(2.5V or 3.3V)
Output Ground
-3-
A
16
50
DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
N.C.
V
DD
N.C.
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin
TQFP
(20mm x 14mm)
DQPb
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
N.C.
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa
November 1999
Rev 3.0
K7A403600M
FUNCTION DESCRIPTION
128Kx36 Synchronous SRAM
The K7A403600M is a synchronous SRAM designed to support the burst address accessing sequence of the P6 and Power PC
based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration
of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS
1
.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa
0
~ DQa
7
and DQPa, WEb controls DQb
0
~ DQb
7
and DQPb, WEc controls DQc
0
~ DQc
7
and DQPc, and WEd control DQd
0
~ DQd
7
and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Case 1
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
0
1
1
Case 2
A
0
1
0
1
0
A
1
1
1
0
0
Case 3
A
0
0
1
0
1
(Interleaved Burst)
Case 4
A
1
1
1
0
0
A
0
1
0
1
0
Fourth Address
BQ TABLE
LBO PIN
LOW
First Address
Case 1
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
1
1
0
Case 2
A
0
1
0
1
0
A
1
1
1
0
0
Case 3
A
0
0
1
0
1
A
1
1
0
0
1
(Linear Burst)
Case 4
A
0
1
0
1
0
Fourth Address
Note :
1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
-4-
November 1999
Rev 3.0
K7A403600M
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS
1
H
L
L
L
L
L
L
L
X
H
X
H
X
H
X
H
CS
2
X
L
X
L
X
H
H
H
X
X
X
X
X
X
X
X
CS
2
X
X
H
X
H
L
L
L
X
X
X
X
X
X
X
X
ADSP ADSC
X
L
L
X
X
L
H
H
H
X
H
X
H
X
H
X
L
X
X
L
L
X
L
L
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
WRITE
X
X
X
X
X
X
L
H
H
H
L
L
H
H
L
L
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
128Kx36 Synchronous SRAM
ADDRESS ACCESSED
N/A
N/A
N/A
N/A
N/A
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
OPERATION
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
Notes :
1. X means "Don′t Care".
2. The rising edge of clock is symbolized by
↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE
GW
H
H
H
H
H
H
L
BW
H
L
L
L
L
L
X
WEa
X
H
L
H
H
L
X
WEb
X
H
H
L
H
L
X
WEc
X
H
H
H
L
L
X
WEd
X
H
H
H
L
L
X
OPERATION
READ
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
Notes :
1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2)
:
OPERATION
Sleep Mode
Read
Write
Deselected
ZZ
H
L
L
L
L
OE
X
L
H
X
X
I/O STATUS
High-Z
DQ
High-Z
Din, High-Z
High-Z
Notes
1. X means "Don
′
t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
-5-
November 1999
Rev 3.0
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