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M74HCT563RM13TR

Description
HCT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, SOP-20
Categorylogic    logic   
File Size287KB,11 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance  
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M74HCT563RM13TR Overview

HCT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, SOP-20

M74HCT563RM13TR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeSOIC
package instructionSOP, SOP20,.4
Contacts20
Reach Compliance Codecompliant
seriesHCT
JESD-30 codeR-PDSO-G20
JESD-609 codee4
length12.8 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.006 A
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Output polarityINVERTED
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP20,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Prop。Delay @ Nom-Sup45 ns
propagation delay (tpd)59 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.5 mm

M74HCT563RM13TR Preview

M74HCT563
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT INVERTING
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 21ns (TYP.) at V
CC
= 4.5V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS :
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 6mA (MIN)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 563
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
M74HCT563B1R
M74HCT563M1R
T&R
M74HCT563RM13TR
M74HCT563TTR
DESCRIPTION
The M74HCT563 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C
2
MOS technology.
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input inversely. When
the LE is taken low, the Q outputs will be latched
inversely at the logic level of D input data.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while OE is at high level the outputs will
be in a high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
The M74HCT563 is designed to directly interface
HSC
2
MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
1/11
M74HCT573
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 3, 4, 5, 6,
7, 8, 9
12, 13, 14,
15, 16, 17,
18, 19
11
10
20
SYMBOL
OE
D0 to D7
Q0 to Q7
NAME AND FUNCTION
3 State Output Enable
Input (Active LOW)
Data Inputs
3 State Latch Outputs
LE
GND
V
CC
Latch Enable Input
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OE
H
L
L
L
LE
X
L
H
H
D
X
X
L
H
OUTPUTS
Q
Z
NO CHANGE (*)
H
L
X: Don’t Care
Z: High Impedance
(*): Q Outputs are latched at the time when the LE input is taken low logic level.
LOGIC DIAGRAM
2/11
M74HCT573
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
35
±
70
500(*)
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
mW
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
P
D
Power Dissipation
T
stg
T
L
Storage Temperature
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
°
C; derate to 300mW by 10mW/
°
C from 65
°
C to 85
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
t
r
, t
f
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time (V
CC
= 4.5 to 5.5V)
Parameter
Value
4.5 to 5.5
0 to V
CC
0 to V
CC
-55 to 125
0 to 500
Unit
V
V
V
°C
ns
3/11
M74HCT573
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
V
CC
(V)
4.5
to
5.5
4.5
to
5.5
4.5
4.5
5.5
5.5
5.5
5.5
I
O
=-20
µA
I
O
=-6.0 mA
I
O
=20
µA
I
O
=6.0 mA
V
I
= V
CC
or GND
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
V
I
= V
CC
or GND
Per Input pin
V
I
= 0.5V or
V
I
= 2.4V
Other Inputs at
V
CC
or GND
T
A
= 25°C
Min.
2.0
Typ.
Max.
Value
-40 to 85°C
Min.
2.0
Max.
-55 to 125°C
Min.
2.0
Max.
V
Unit
V
IH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
Additional Worst
Case Supply
Current
V
IL
0.8
4.4
4.18
4.5
4.31
0.0
0.17
0.1
0.26
±
0.1
±
0.5
4
2.0
4.4
4.13
0.8
4.4
4.10
0.1
0.33
±
1
±
5
40
2.9
0.8
V
V
OH
V
OL
I
I
I
OZ
V
0.1
0.40
±
1
±
10
80
3.0
V
µA
µA
µA
mA
I
CC
I
CC
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6ns)
Test Condition
Symbol
Parameter
V
CC
(V)
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
C
L
(pF)
50
50
150
50
150
50
150
50
50
50
50
T
A
= 25°C
Min.
Typ.
7
21
25
19
23
19
23
18
7
4
Max.
12
33
39
30
36
30
36
25
15
10
5
Value
-40 to 85°C
Min.
Max.
15
41
49
38
45
38
45
31
19
13
5
-55 to 125°C
Min.
Max.
18
50
59
45
54
45
54
38
22
15
5
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
TLH
t
THL
Output Transition
Time
t
PLH
t
PHL
Propagation Delay
Time (LE - Q)
t
PLH
t
PHL
Propagation Delay
Time (D - Q)
t
PZL
t
PZH
Output Enable
Time
t
PLZ
t
PHZ
Output Disable
Time
t
W(L)
Minimum Pulse
Width (LE)
t
W(H)
t
s
t
h
Minimum Set-Up
Time
Minimum Hold
Time
R
L
= 1 K
R
L
= 1 K
4/11
M74HCT573
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
T
A
= 25°C
Min.
Typ.
5
10
51
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
pF
Unit
C
IN
C
OUT
C
PD
Input Capacitance
Output
Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per Latch)
TEST CIRCUIT
TEST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
C
L
= 50pF/150pF or equivalent (includes jig and probe capacitance)
R
1
= 1KΩ or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
SWITCH
Open
V
CC
GND
5/11

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