3D3215M-12 datasheet, PDF - EEWORLD Datasheet

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3D3215M-12: Description300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit; Categorylogic logic; File Size128KB，4 Pages; ManufacturerData Delay Devices

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3D3215M-12 Overview

300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit

3D3215M-12 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Data Delay Devices
Parts packaging code	DIP
package instruction	DIP, DIP8,.3
Contacts	8
Reach Compliance Code	compliant
Input frequency maximum value (fmax)	5.56 MHz
JESD-30 code	R-PDIP-T8
length	9.65 mm
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	1
Number of taps/steps	5
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP8,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Maximum supply current (ICC)	2 mA
programmable delay line	NO
Prop。Delay @ Nom-Sup	60 ns
Certification status	Not Qualified
Maximum seat height	4.58 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	60 ns
width	7.62 mm
Base Number Matches	1

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3D3215

MONOLITHIC 5-TAP 3.3V

FIXED DELAY LINE

(SERIES 3D3215)

FEATURES

•

All-silicon, low-power 3.3V CMOS technology

Vapor phase, IR and wave solderable

Auto-insertable (DIP pkg.)

Low ground bounce noise

Leading- and trailing-edge accuracy

Delay range:

1.5ns through 300ns

Total delay tolerance:

2% or 0.5ns (3.3V, 25C)

Temperature stability:

±1%

typical (0C-70C)

Vdd stability:

±1%

typical (3.0V-3.6V)

Static Idd:

1.3ma typical

Minimum input pulse width:

25% of total delay

GND

PACKAGES

VDD

GND

VDD

3D3215Z-xx

SOIC (150 Mil)

3D3215M-xx

DIP (300 Mil)

For mechanical dimensions, click

here

For package marking details, click

here

FUNCTIONAL DESCRIPTION

The 3D3215 5-Tap Delay Line product family consists of fixed-delay

3.3V CMOS integrated circuits. Each package contains a single delay

line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-

tap (incremental) delay values can range from 1.5ns through 60ns. The

input is reproduced at the outputs without inversion, shifted in time as

per the user-specified dash number. The 3D3215 is 3.3V CMOS-

compatible and features both rising- and falling-edge accuracy.

PIN DESCRIPTIONS

VDD

GND

N/C

Delay Line Input

Tap 1 Output (20%)

Tap 2 Output (40%)

Tap 3 Output (60%)

Tap 4 Output (80%)

Tap 5 Output (100%)

+3.3 Volts

Ground

No Connection

The all-CMOS 3D3215 integrated circuit has been designed as a

reliable, economic alternative to hybrid fixed delay lines. It is offered in

a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.

TABLE 1: PART NUMBER SPECIFICATIONS

DASH #

3D3215Z-xx

3D3215M-xx

-1.5

-2

-2.5

-3

-4

-5

-6

-8

-10

-12

-15

-20

-25

-30

-40

-50

-60

DELAY SPECIFICATIONS

TOTAL

TAP-TAP

DELAY (ns)

6.0

0.5*

1.5

0.7

8.0

0.5*

2.0

0.8

10.0

0.5*

2.5

1.0

12.0

0.5*

3.0

1.3

16.0

0.5*

4.0

1.3

20.0

0.5*

5.0

1.4

24.0

0.5*

6.0

1.4

40.0

0.8

8.0

1.4

50.0

1.0

10.0

1.5

60.0

1.2

12.0

1.5

75.0

1.5

15.0

1.5

100

2.0

20.0

2.0

125

2.5

25.0

2.5

150

3.0

30.0

3.0

200

4.0

40.0

4.0

250

5.0

50.0

5.0

300

6.0

60.0

6.0

INPUT RESTRICTIONS

RECOMMENDED

ABSOLUTE

Max Freq

Min P.W.

Max Freq

Min P.W.

23.8 MHz

21.0 ns

83.3 MHz

6.00 ns

20.8 MHz

24.0 ns

83.3 MHz

6.00 ns

18.5 MHz

27.0 ns

66.7 MHz

7.50 ns

16.7 MHz

30.0 ns

55.6 MHz

9.00 ns

13.9 MHz

36.0 ns

50.0 MHz

10.00 ns

11.9 MHz

42.0 ns

40.0 MHz

12.50 ns

10.4 MHz

48.0 ns

55.6 MHz

9.00 ns

8.33 MHz

60.0 ns

41.7 MHz

12.00 ns

6.67 MHz

75.0 ns

40.0 MHz

12.50 ns

5.56 MHz

90.0 ns

33.3 MHz

15.00 ns

4.42 MHz

113 ns

26.7 MHz

18.75 ns

3.33 MHz

150 ns

20.0 MHz

25.00 ns

2.66 MHz

188 ns

16.0 MHz

31.25 ns

2.22 MHz

225 ns

13.3 MHz

37.50 ns

1.67 MHz

300 ns

10.0 MHz

50.00 ns

1.33 MHz

375 ns

8.0 MHz

62.50 ns

1.11 MHz

450 ns

6.7 MHz

75.00 ns

* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns

1.5ns

NOTE: Any dash number between 1.5 and 60 not shown is also available as standard

2001

Data Delay Devices

Doc #01014

12/3/01

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

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