3D6701
MONOLITHIC CLOCK
SYNCHRONIZER
(SERIES 3D6701)
FEATURES
Synchronizes free-running clock to external gate signal
Input frequency range:
30MHz through 100MHz
Phase resolution:
200ps typical
Output frequency:
Programmable from F
IN
to F
IN
/256
Output period jitter:
Equal to jitter of clock source
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
For mechanical dimensions, click
here
.
For package marking details, click
here
.
VDD
PINOUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
SEL
D1
D3
D5
D7
F
OUT
D0
D2
D4
D6
G
IN
GND
F
IN
GND
3D6701
DIP-14
3D6701D SOIC-14
FUNCTIONAL DESCRIPTION
One major drawback to using a crystal oscillator for frequency generation
is that the phase of the generated clock signal cannot be synchronized to
an external timing event. A delay-line oscillator (eg, the 3D7701), while
supporting this feature, cannot provide the stability and jitter performance
of a crystal. The 3D6701 clock synchronizer provides the best of both
worlds. The device accepts two inputs – a stable frequency source and a
gate signal – and matches the phase of the clock to the gate. It also
provides 8 bits of frequency scaling at the device output. The 3D6701
can be operated at 5V or 3.3V, and is offered in both a 16-pin DIP and a
space-saving 16-pin SOIC package.
PIN DESCRIPTIONS
F
IN
Clock Input
G
IN
Gate Input
D0-D7 Divisor Inputs
SEL VDD Select Input
F
OUT
Sync Oscillator Out
VDD +3.3 or +5 Volts
GND Ground
FIN
(Async)
GIN
D
INH
OUT
(D=0)
OUT
(D=1)
OUT
(D=2)
T
RES
Figure 1: Timing Diagram
2014
Data Delay Devices
Doc #14015
6/9/2014
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D6701
THEORY OF OPERATION
The 3D6701 clock synchronizer architecture is
shown in Figure 2. The F
IN
input is assumed to
come from a stable clock source, such as a
crystal oscillator. A rising edge on the G
IN
input
initiates the phase detection process. Once the
phase of the clock with respect to the gate has
been resolved, a delay line is adjusted to match
the phases of the two signals.
There is a finite resolution to the phase detection
process (typically under 500ps), so that, from one
gate trigger to the next, there will remain some
residual gate-to-output jitter. However, for a given
gate, the jitter from one clock cycle to the next is
equal to the jitter of the reference clock itself.
The 3D6701 also contains a programmable
divider that reduces the output frequency by an
amount given by the D7:0 inputs. F
OUT
is given by
F
IN
/ (D+1), so that the output frequency may
range from F
IN
(D=0) to F
IN
/ 256 (D=255). When
G
IN
returns low, the output returns to a low level
and remains there until the next rising edge of
G
IN
.
The performance of CMOS integrated circuits is
strongly dependent on power supply stability. It is
essential that the power supply pins be
adequately bypassed and filtered. In addition, the
power bus should be of as low an impedance
construction as possible. Power planes are
preferred.
When operating at 3.3V, tie the SEL input to
GND. When operating at 5.0V, tie the SEL
input to VDD.
G
IN
Phase
Resolver
F
IN
Programmable
Delay Line
8-Bit
Divider
F
OUT
D7:0
Figure 2: 3D6701 Functional Block Diagram
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
V
DD
+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
Doc #14015
6/9/2014
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
3D6701
DEVICE SPECIFICATIONS (Cont’d)
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
Low Level Output Current
SYMBOL
I
DD
V
IH
V
IL
I
IH
I
IL
I
OH
I
OL
MIN
2.0
0.8
1.0
1.0
-4.0
TYP
20.0
MAX
UNITS
mA
V
V
A
A
mA
mA
NOTES
4.0
-35.0
15.0
V
IH
= V
DD
V
IL
= 0V
V
DD
=4.75V, V
OH
=2.4V
V
DD
=4.75V, V
OL
=0.4V
*I
DD
will vary slightly for different input clock frequencies
TABLE 3: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
Input Frequency
Duty Cycle
Gate Frequency
Gate Inactive (Low)
Gate-to-Out Delay
SYMBOL
F
IN
DC(F
IN
)
G
IN
G
IN,LOW
D
INH
ΔD
INH
MIN
30
40
200
157
136
120
420
460
780
50
T
RES
10
TYP
MAX
80
60
1
UNITS
MHz
%
MHz
ns
ns
ns
ns
ps
ps
ps
ps
ns
NOTES
Gate-to-Out Delay
Jitter
F
OUT
Period Jitter
Reset Time
F
IN
=50MHz
F
IN
=62MHz
F
IN
=80MHz
F
IN
=50MHz
F
IN
=62MHz
F
IN
=80MHz
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
Input Frequency
Duty Cycle
Gate Frequency
Gate Inactive (Low)
Gate-to-Out Delay
SYMBOL
F
IN
DC(F
IN
)
G
IN
G
IN,LOW
D
INH
ΔD
INH
MIN
50
40
125
138
118
106
640
700
520
50
T
RES
10
TYP
MAX
100
60
2
UNITS
MHz
%
MHz
ns
ns
ns
ns
ps
ps
ps
ps
ns
NOTES
Gate-to-Out Delay
Jitter
F
OUT
Period Jitter
Reset Time
F
IN
=50MHz
F
IN
=62MHz
F
IN
=80MHz
F
IN
=50MHz
F
IN
=62MHz
F
IN
=80MHz
Doc #14015
6/9/2014
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D6701
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
o
o
Ambient Temperature:
25 C
3 C
Supply Voltage (Vcc):
5.0V
0.1V
Input Pulse:
High = 3.0V
0.1V
Low = 0.0V
0.1V
Source Impedance:
50 Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6 and 2.4V)
OUTPUT:
R
load
:
C
load
:
Threshold:
10K
10%
5pf
10%
1.5V (Rising & Falling)
Device
Under
Test
10K
Digital
Scope
5pf
470
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
REF
PULSE
GENERATOR
OUT
TRIG
G
IN
F
IN
DEVICE UNDER
TEST (DUT)
F
OUT
IN
TRIG
FREQUENCY/
TIME INTERVAL COUNTER
FREQ SOURCE
Figure 3: Test Setup
T
RISE
G
IN
2.4V
1.5V
0.6V
T
FALL
V
IH
2.4V
1.5V
0.6V
V
IL
D
INH
F
OUT
1.5V
1/F
OSC
1.5V
T
RES
1.5V
Figure 4: Timing Diagram
Doc #14015
6/9/2014
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
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