3D7702
MONOLITHIC GATED
DELAY LINE OSCILLATOR
(SERIES 3D7702)
FEATURES
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•
•
•
•
•
•
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All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Frequency range:
0.3MHz through 100MHz
Frequency tolerance:
0.5% typical
Temperature stability:
±1.5%
typical (-40C to 85C)
Vdd stability:
±0.5%
typical (4.75V to 5.25V)
14-pin DIP available as drop-in replacements for
hybrid delay line oscillator (DLO32F)
O1
NC
NC
GND
1
2
3
4
8
7
6
5
PACKAGES
VDD
NC
O2
EN
O1
NC
NC
NC
NC
NC
GND
3D7702-xx
3D7702K-xx
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
NC
NC
NC
O2
NC
EN
3D7702Z-xx SOIC-8
DIP-14
NC pins removed
For mechanical dimensions, click
here
.
For package marking details, click
here
.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7702 Delay Line Oscillator product family consists of fixed-
EN
Oscillator Enable
frequency CMOS integrated circuit oscillators. Each package contains a
O1
Oscillator Output 1
single oscillator, which is gated and can therefore be synchronized to an
O2
Oscillator Output 2
external signal. The device frequency can range from 0.3MHz through
VDD +5 Volts
100MHz. The 3D7702 has two outputs that are 180° out-of-phase when
GND Ground
the oscillator is running, and can be used as a drop-in replacement for
the DLO32F hybrid oscillator. The 3D7702 is TTL- and CMOS-compatible, capable of driving ten 74LS-type
loads. It is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC
package.
Doc #06024
12/5/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7702
TABLE 1: PART NUMBER SPECIFICATIONS
DASH
NUMBER
-0.3
-0.4
-0.5
-0.75
-1
-2
-2.5
-3
-4
-5
-7.5
-10
-20
-25
-30
-40
-50
-75
-100
NOTE:
OUTPUT FREQUENCY (MHz)
25C
-40C to 85C
Vdd=5.00V
4.75<Vdd<5.25
0.3
±
0.002
0.3
±
0.008
0.4
±
0.002
0.4
±
0.010
0.5
±
0.003
0.5
±
0.013
0.75
±
0.004
0.75
±
0.019
1.0
±
0.005
1.0
±
0.025
2.0
±
0.010
2.0
±
0.050
2.5
±
0.013
2.5
±
0.063
3.0
±
0.015
3.0
±
0.075
4.0
±
0.020
4.0
±
0.100
5.0
±
0.025
5.0
±
0.125
7.5
±
0.038
7.5
±
0.188
10.0
±
0.05
10.0
±
0.25
20.0
±
0.10
20.0
±
0.50
25.0
±
0.13
25.0
±
0.63
30.0
±
0.15
30.0
±
0.75
40.0
±
0.20
40.0
±
1.00
50.0
±
0.25
50.0
±
1.25
75.0
±
0.38
75.0
±
3.75
100.0
±
0.50
100.0
±
7.00
2006
Data Delay Devices
Any dash number between 0.3 and 100 not shown is also available as standard.
Doc #06024
12/5/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
3D7702
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D7702 delay line oscillator architecture is
shown in Figure 1. The internal delay line is
composed of a number of delay cells connected
in series and is compensated for thermal and
supply voltage variations. A low-going edge on
the EN input starts the oscillator, with the O2
output responding immediately. The O1 output is
delayed by ½ cycle. The response of the output
when the oscillator is disabled depends on the
status of O2 when the EN signal goes high, as
shown in Figure 2. If O2 is low, it will remain low,
and the final pulse on O1 will be ½ of the period.
If O2 is high, it will go low as soon as EN goes
high, and the final pulse on both outputs will have
a width smaller than ½ the period.
VDD
GND
Temp & Vdd
Compensation
O1
Delay Line
O2
EN
Figure 1: 3D7702 Functional Diagram
EN
5ns typ
O2
O1
EN
5ns typ
5ns typ
O2
O1
Figure 2: 3D7702 Timing Diagrams
Doc #06024
12/5/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7702
APPLICATION NOTES (CONT’D)
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7702 oscillator utilizes novel
and innovative compensation circuitry to
minimize the frequency variations induced by
fluctuations in power supply and/or temperature.
The thermal coefficient is reduced to 250 PPM/C,
which is equivalent to a variation, over the -40C
to 85C operating range, of
±1.5%
from the room-
temperature frequency setting. The power supply
coefficient is reduced, over the 4.75V to 5.25V
operating range, to
±0.5%
of the frequency
setting at the nominal 5.0VDC power supply.
These specifications hold for the lower
frequencies only. For higher dash numbers, the
variations will be slightly greater, as noted in
Table 1.
It is essential that the power supply
pin be adequately bypassed and filtered. In
addition, the power bus should be of as low
an impedance construction as possible.
Power planes are preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
V
DD
+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output
Current
Low Level Output Current
Output Rise & Fall Time
SYMBOL
I
DD
V
IH
V
IL
I
IH
I
IL
I
OH
I
OL
T
R
& T
F
MIN
2.0
0.8
1.0
1.0
-4.0
TYP
3.5
MAX
5.5
UNITS
mA
V
V
µA
µA
mA
mA
2.5
ns
NOTES
-35.0
4.0
15.0
2.0
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
*I
DD
(Dynamic) = 2 * C
LD
* V
DD
* F
where: C
LD
= Average capacitance load/output (pf)
F = Device frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
Doc #06024
12/5/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
3D7702
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
5.0V
±
0.1V
Input Pulse:
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V
)
OUTPUT:
R
load
:
C
load
:
Threshold:
10KΩ
±
10%
5pf
±
10%
1.5V (Rising & Falling)
Device
Under
Test
10KΩ
5pf
Digital
Scope
470Ω
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
O1
PULSE
GENERATOR
OUT
TRIG
EN
DEVICE UNDER
TEST (DUT)
O2
REF
IN
TRIG
FREQUENCY/
TIME INTERVAL COUNTER
Figure 3: Test Setup
t
FALL
EN
2.4V
1.5V
0.6V
t
RISE
V
IL
1/f
OSC
1.5V
2.4V
V
IH
1.5V
0.6V
t
ENB
O2
1.5V
t
DIS
1.5V
Figure 4: Timing Diagram
Doc #06024
12/5/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
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