DATA SHEET
2GB DDR3 SDRAM SO-DIMM
EBJ21UE8BBS0 (256M words
×
64 bits, 2 Ranks)
Specifications
•
Density: 2GB
•
Organization
256M words
×
64 bits, 2 ranks
•
Mounting 16 pieces of 1G bits DDR3 SDRAM sealed
in FBGA
•
Package: 204-pin socket type small outline dual in
line memory module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant) and Halogen-free
•
Power supply: VDD
=
1.5V
±
0.075V
•
Data rate: 1333Mbps/1066Mbps/800Mbps (max.)
•
Eight internal banks for concurrent operation
(components)
•
Interface: SSTL_15
•
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
•
/CAS Latency (CL): 6, 7, 8, 9
•
/CAS write latency (CWL): 5, 6, 7
•
Precharge: auto precharge option for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
TC = 0°C to +95°C
Features
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
On-Die-Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
•
Multi Purpose Register (MPR) for temperature read
out
•
ZQ calibration for DQ drive and ODT
•
Programmable Partial Array Self-Refresh (PASR)
•
/RESET pin for Power-up sequence and reset
function
•
SRT range:
Normal/extended
•
Programmable Output driver impedance control
Document No. E1377E30 (Ver. 3.0)
Date Published April 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2008-2009
EBJ21UE8BBS0
Pin Description
Pin name
A0 to A13
A10 (AP)
A12 (/BC)
BA0, BA1, BA2
DQ0 to DQ63
/RAS
/CAS
/WE
/CS0, /CS1
CKE0, CKE1
CK0, CK1
/CK0, /CK1
DQS0 to DQS7, /DQS0 to /DQS7
DM0 to DM7
SCL
SDA
SA0, SA1
VDD
VDDSPD
VREFCA
VREFDQ
VSS
VTT
/RESET
ODT0, ODT1
NC
Function
Address input
Row address
Column address
Auto precharge
Burst chop
Bank select address
Data input/output
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Reference voltage for CA
Reference voltage for DQ
Ground
I/O termination supply for SDRAM
Set DRAM to known state
ODT control
No connection
A0 to A13
A0 to A9
Data Sheet E1377E30 (Ver. 3.0)
5
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