Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
FEATURES
flip-flops
•
High speed parallel registers with positive edge-triggered D-type
•
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
DESCRIPTION
The 74ABT823 Bus interface Register is designed to eliminate the
extra packages required to buffer existing registers and provide
extra data width for wider data/address paths of buses carrying
parity.
The 74ABT823 is a 9-bit wide buffered register with Clock Enable
(CE) and Master Reset (MR) which are ideal for parity bus
interfacing in high microprogrammed systems.
The register is fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per Jedec Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
•
Power-up 3-State
•
Power-up Reset
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
CP to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled;
V
O
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
TYPICAL
4.4
4
7
500
UNIT
ns
pF
pF
nA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT823 N
74ABT823 D
74ABT823 DB
74ABT823 PW
NORTH AMERICA
74ABT823 N
74ABT823 D
74ABT823 DB
74ABT823PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
OE
D0-D8
Q0-Q8
CP
CE
MR
GND
V
CC
FUNCTION
Output enable input
(active-Low)
Data inputs
Data outputs
Clock pulse input (active
rising edge)
Clock enable input
(active-Low)
Master reset input
(active-Low)
Ground (0V)
Positive supply voltage
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
TOP VIEW
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CE
CP
1
2, 3, 4, 5, 6,
7, 8, 9, 10
23, 22, 21, 20,
19,18, 17, 16, 15
13
14
11
12
24
D8 10
MR 11
GND 12
SA00227
1995 Sep 06
1
853–1617 15703
Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1
11
2
3
4
5
6
7
8
9
10
14
13
D0 D1 D2 D3 D4 D5 D6 D7 D8
13
14
11
1
CP
CE
MR
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
2
3
4
5
6
7
23 22 21 20 19 18 17 16 15
8
9
10
EN
R
G1
1C2
2D
23
22
21
20
19
18
17
16
15
SA00228
SA00229
FUNCTION TABLE
INPUTS
OE
L
L
L
L
H
H
h
L
l
MR
L
H
H
H
X
CE
X
L
L
H
X
CP
X
↑
↑
↑
X
Dn
X
h
l
X
X
OUTPUTS
Q0 – Q8
L
H
L
NC
Z
Hold
High impedance
NC
X
Z
↑
↑
=
=
=
=
=
No change
Don’t care
High impedance “off” state
Low to High clock transition
Not a Low-to-High clock transition
Clear
Load and read data
OPERATING MODE
= High voltage level
= High voltage level one set-up time prior to the Low-to-High
clock transition
= Low voltage level
= Low voltage level one set-up time prior to the Low-to-High
clock transition
LOGIC DIAGRAM
14
CE
D0
2
13
CP
CP
D
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D8
10
R
Q
R
Q
R
Q
RR Q
R
Q
R
Q
R
Q
R
Q
R
Q
11
MR
1
OE
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
SA00230
1995 Sep 06
2
Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
Min
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
4.5
0
2.0
0.8
–32
64
5
+85
LIMITS
Max
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
1995 Sep 06
3
Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
Min
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
OH
High-level output voltage
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
V
OL
V
RST
I
I
I
OFF
I
PU
/I
PD
I
OZH
I
OZL
I
CEX
I
O
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current per
input pin
2
Quiescent supply current
Low-level output voltage
Power-up output low
voltage
3
Input leakage current
Power-off leakage current
Power-up/down 3-State
output current
4
3-State output High current
3-State output Low current
Output High leakage current
Output current
1
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 2.0V; V
O
= 0.5V; V
OE
= V
CC
;
V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
–50
2.5
3.0
2.0
Typ
–0.9
2.9
3.4
2.4
0.42
0.13
±0.01
±5.0
±5.0
5.0
–5.0
5.0
–100
0.5
27
0.5
0.5
0.55
0.55
±1.0
±100
±50
50
–50
50
–180
250
34
250
1.5
–50
Max
–1.2
2.5
3.0
2.0
0.55
0.55
±1.0
±100
±50
50
–50
50
–180
250
34
250
1.5
T
amb
= –40°C
to +85°C
Min
Max
–1.2
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
mA
UNIT
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. For V
CC
= 2.1V to V
CC
= 5V
"
10%, a
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Min
f
MAX
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum clock frequency
Propagation delay
CP to Qn
Propagation delay
MR to Qn
Output enable time
to High and Low level
Output disable time
from High and Low level
1
1
2
4
5
4
5
125
2.1
2.2
2.0
1.0
2.2
2.7
2.8
T
amb
= +25
o
C
V
CC
= +5.0V
Typ
200
4.3
4.4
4.1
3.0
4.1
4.8
5.0
5.9
6.1
6.3
4.5
5.6
6.2
6.4
Max
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
±0.5V
Min
125
2.1
2.2
2.0
1.0
2.2
2.7
2.8
6.8
6.7
7.1
5.3
6.3
6.9
6.9
Max
MHz
ns
ns
ns
ns
UNIT
1995 Sep 06
4
Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(L)
t
rec
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
CP pulse width
High or Low
Setup time, High or Low
CE to CP
Hold time, High or Low
CE to CP
MR pulse width, Low
Recovery time
MR to CP
3
3
1
3
3
2
2
2.1
2.1
1.3
1.3
2.9
3.8
2.0
3.3
1.0
2.0
5.5
2.5
Typ
0.5
0.2
0.0
–0.3
1.9
2.8
–0.5
1.5
–1.4
0.7
4.0
0.6
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
±0.5V
Min
2.1
2.1
1.3
1.3
2.9
3.8
2.0
3.3
1.0
2.0
5.5
2.5
ns
ns
ns
ns
ns
ns
ns
UNIT
1995 Sep 06
5
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