FemtoClock
®
NG Crystal-to-3.3V LVPECL
Clock Generator
ICS843N3960I
DATA SHEET
General Description
The ICS843N3960I is a LVPECL Clock Synthesizer. The
ICS843N3960I can synthesize 100MHz, 125MHz, 156.25MHz and
212.5MHz from a single 25MHz crystal or reference clock.
Utilizing an external loop filter capacitor, the ICS843N3960I is
capable of holdover mode when the main reference clock becomes
unstable, making this ideal for redundant timing applications.
Features
•
•
•
•
•
•
•
•
•
•
•
Fourth Generation FemtoClock® NG PLL technology
Two differential LVPECL outputs
Crystal oscillator interface designed for 12pF, 25MHz parallel
resonant crystal
CLK/nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
RMS phase jitter at 100MHz (12kHz – 20MHz): 0.510ps (max.)
RMS phase jitter at 125MHz (12kHz – 20MHz): 0.575ps (max.)
RMS phase jitter at 156.25MHz (12kHz – 20MHz):
0.504ps (max.)
RMS phase jitter at 212.5MHz (12kHz – 20MHz): 0.512ps (max.)
3.3V power supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
OE
Pullup
Pin Assignment
LOR
CLK_ SEL
Pulldown
XTAL_IN
25 MHz
XTAL_OUT
Xtal
Osc.
0
CLK
nCLK
Pullup
25MHz
Pullup /
Pulldown
LOR
1
Phase
Detector
+
Charge
Pump
Q0
FemtoClock NG
VCO
nQ0
/N
FSEL_0
FSEL_1
OE
Q1
nQ1
V
EE
CP
V
EE
nCLK
CLK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
V
CCA
V
CC
Q0
nQ0
LOR
V
EE
CLK_SEL
XTAL_IN
XTAL_OUT
Q1
nQ 1
/M
FSEL _0
Pulldown
FSEL _1
Pulldown
Divider
Control
Logic
ICS843N3960I
20 Lead TSSOP, E-Pad
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
ICS843N3960DGI REVISION B SEPTEMBER 24, 2012
CP
1
©2012 Integrated Device Technology, Inc.
ICS843N3960I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1, 2
3
4, 5
6, 8, 14
7
9
10
11, 12
13
15
16, 17
18, 20
19
Name
FSEL0,
FSEL1
OE
Q1, nQ1
V
EE
CP
nCLK
CLK
XTAL_OUT
XTAL_IN
CLK_SEL
LOR
nQ0, Q0
V
CC
V
CCA
Input
Input
Output
Power
Output
Input
Input
Input
Input
Output
Output
Power
Power
Pulldown
Pullup/
Pulldown
Pulldown
Type
Pulldown
Pullup
Description
Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3A.
Active HIGH output enable. LVCMOS/LVTTL interface levels.
Differential output pair. 3.3V LVPECL interface levels.
Negative supply pins.
External loop filter capacitor output pin.
Inverting differential clock input. Internal resistor bias to V
CC
/2.
Non-inverting differential clock input.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Input source control pin. LVCMOS/LVTTL interface levels. See Table 3C.
Loss of Reference output pin. See LOR Functionality section.
Differential output pair. 3.3V LVPECL interface levels.
Core supply pins.
Analog supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
R
OUT
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Output Impedance
LOR
Test Conditions
Minimum
Typical
3.5
51
51
18
Maximum
Units
pF
k
Ω
k
Ω
Ω
ICS843N3960DGI REVISION B SEPTEMBER 24, 2012
2
©2012 Integrated Device Technology, Inc.
ICS843N3960I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Function Tables
Table 3A. Output Frequency Table
FSEL_1
0 (default)
0
1
1
FSEL_0
0 (default)
1
0
1
M Divider
80
100
80
85
N Divider
20
16
16
10
Output Frequencies (MHz)
100
156.25
125
212.5
Table 3B. Output Enable & Clock Enable Function Table
Control Input
OE
0
1 (default)
Q0, nQ0
High-Impedance
Enabled
Output
Q1, nQ1
High-Impedance
Enabled
Table 3C. CLK_SEL Function Table
Control Input
CLK_SEL
0 (default)
1
Input Select
Crystal Interface
CLK, nCLK selected
LOR Functionality
The ICS843N3960I has a Loss of Reference (LOR) output that is
used to indicate when the input reference has been lost, resulting in
a logic high value on the LOR output. The LOR output is set high
when the input clock experiences a single missed clock edge, or is
completely lost. Once the input clock is recovered, the LOR output is
set back to its low state.
The LOR output pin is deemed in be in a valid state 100ms after the
device has been powered up and the FemtoClock ® NG VCO is
phase locked.
NOTE: The LOR output pin will not accurately reflect the state of the
input if the device is powered up without an input clock present or
properly selected through the input mux interface (CLK_SEL). If this
condition occurs, the device must be power cycled to reset the LOR
circuitry.
Holdover Behavior
The ICS843N3960 has a holdover function. Holdover is
accomplished by putting the charge pump in a high impedance state
after the LOR output has been asserted high. This mode provides a
stable output frequency even when the primary reference has been
lost.
During holdover mode, the charge pump is placed in a high
impedance state and the external charge pump capacitor, CP, is used
to keep the internal VCO tuning voltage steady. Due to leakage
current on this capacitor, the VCO accuracy, in terms of PPM, will
vary over time. By using a 100uF capacitor on CP, the ICS843N3960I
can achieve holdover accuracy of 275ppm over a ten second period.
Note that holdover accuracy can only be achieved when the input
reference clock has been stable for longer than 1ms.
ICS843N3960DGI REVISION B SEPTEMBER 24, 2012
3
©2012 Integrated Device Technology, Inc.
ICS843N3960I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
3.63V
0V to 2V
-0.5V to V
CC
+ 0.5V
50mA
100mA
34.3°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CCA
I
CCA
I
EE
Parameter
Core Supply Voltage
Analog Supply Voltage
Analog Supply Current
Power Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.16
Typical
3.3
3.3
Maximum
3.465
3.465
16
122
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
OE
Input High Current
FSEL[1:0],
CLK_SEL
OE
I
IL
V
OH
V
OL
Input Low Current
FSEL[1:0],
CLK_SEL
LOR
LOR
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.3V ± 5%, I
OH
= -12mA
V
CC
= 3.3V ± 5%, I
OL
= 12mA
-150
-5
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
Output High Voltage
Output Low Voltage
ICS843N3960DGI REVISION B SEPTEMBER 24, 2012
4
©2012 Integrated Device Technology, Inc.
ICS843N3960I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Table 4C. Differential DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
CLK, nCLK
nCLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
0.15
V
EE
+ 0.5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1: Common mode voltage is defined as crossing point.
Table 4D. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CC
– 2V.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
50
7
12
MHz
Maximum
Units
Ω
pF
pF
ICS843N3960DGI REVISION B SEPTEMBER 24, 2012
5
©2012 Integrated Device Technology, Inc.
京公网安备 11010802033920号
EEWORLD
