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Document Number: 38-07290 Rev. *H
Page 2 of 14
CY29972
Pin Configuration
Figure 1. 52-pin TQFP pinout
VCO_SEL
SELA0
SELA1
SELB0
SELB1
VDDC
VDDC
QA0
QA2
QA3
QA1
52 51 50 49 48 47 46 45 44 43 42 41 40
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
XIN
XOUT
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
14 15 16 17 18 19 20 21 22 23 24 25 26
INV_CLK
VSS
QC3
VDDC
QC2
SELC1
SELC0
QC1
VDDC
QC0
VSS
SYNC
FB_SEL1
VSS
CY29972
VSS
Document Number: 38-07290 Rev. *H
Page 3 of 14
CY29972
Pin Description
Pin
[2]
11
12
9
10
44, 46, 48, 50
32, 34, 36, 38
16, 18, 21, 23
29
Name
X
IN
X
OUT
T
CLK0
T
CLK1
QA(3:0)
QB(3:0)
QC(3:0)
FB_OUT
PWR
–
–
–
–
V
DDC
V
DDC
V
DDC
V
DDC
I/O
I
O
I
I
O
O
O
O
Type
–
–
PU
PU
–
–
–
–
Description
Oscillator input.
Connect to a crystal.
Oscillator output.
Connect to a crystal.
External reference/test clock input.
External reference/test clock input.
Clock outputs.
See
Table 2 on page 5
for frequency selections.
Clock outputs.
See
Table 2 on page 5
for frequency selections.
Clock outputs.
See
Table 2 on page 5
for frequency selections.
Feedback clock output.
Connect to FB_IN for normal operation. The divider
ratio for this output is set by FB_SEL(0:2). See
Table 1 on page 1.
A bypass
delay capacitor at this output will control Input Reference/ Output Banks phase
relationships.
Synchronous pulse output.
This output is used for system synchronization.
The rising edge of the output pulse is in sync with both the rising edges of
QA(0:3) and QC(0:3) output clocks regardless of the divider ratios selected.
Frequency select inputs.
These inputs select the divider ratio at QA(0:3)
outputs. See
Table 2 on page 5.
Frequency select inputs.
These inputs select the divider ratio at QB(0:3)
outputs. See
Table 2 on page 5.
Frequency select inputs.
These inputs select the divider ratio at QC(0:3)
outputs. See
Table 2 on page 5.
Feedback select inputs.
These inputs select the divide ratio at FB_OUT
output. See
Table 1 on page 1.
VCO divider select input.
When set LOW, the VCO output is divided by 2.
When set HIGH, the divider is bypassed. See
Table 1 on page 1.
Feedback clock input.
Connect to FB_OUT for accessing the PLL.
PLL enable input.
When asserted HIGH, PLL is enabled; when LOW, PLL is
bypassed.
Reference select input.
When HIGH, the crystal oscillator is selected; when
LOW, TCLK (0,1) is the reference clock.
TCLK select input.
When LOW, TCLK0 is selected and when HIGH TCLK1
is selected.
Master reset/output enable input.
When asserted LOW, resets all of the
internal flip-flops and also disables all of the outputs. When pulled high,
releases the internal flip-flops from reset and enables all of the outputs.
Inverted clock input.
When set HIGH, QC(2,3) outputs are inverted. When
set LOW, the inverter is bypassed.
Serial clock input.
Clocks data at SDATA into the internal register.
Serial data input.
Input data is clocked to the internal register to enable/disable
individual outputs. This provides flexibility in power management.
3.3 V power supply for output clock buffers.
3.3 V power supply for PLL.
Common ground.
25
SYNC
V
DDC
–
–
–
–
–
–
–
–
–
–
O
–
42, 43
40, 41
19, 20
5, 26, 27
52
31
6
7
8
2
SELA(1,0)
SELB(1,0)
SELC(1,0)
FB_SEL(2:0)
VCO_SEL
FB_IN
PLL_EN
REF_SEL
TCLK_SEL
MR#/OE
I
I
I
I
I
I
I
I
I
I
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
14
3
4
17, 22, 28,
33,37, 45, 49
13
1, 15, 24, 30,
35, 39, 47, 51
INV_CLK
S
CLK
S
DATA
V
DDC
V
DD
V
SS
–
–
–
–
–
–
I
I
I
–
–
–
PU
PU
PU
–
–
–
Note
2. A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Document Number: 38-07290 Rev. *H
Page 4 of 14
CY29972
Description
The CY29972 has an integrated PLL that provides low skew and
low jitter clock outputs for high-performance microprocessors.
Three independent banks of four outputs and an independent
PLL feedback output (FB_OUT) provide exceptional flexibility for
possible output configurations. The PLL is ensured stable
operation given that the V
CO
is configured to run between
200 MHz and 480 MHz. This allows a wide range of output
frequencies up to 125 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input (FB_IN) is connected to the feedback output
(FB_OUT). The internal V
CO
is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select inputs
(refer to Frequency Table). The V
CO
frequency is then divided to
provide the required output frequencies. These dividers are set
by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see the
following Table). For situations were the V
CO
needs to run at
relatively low frequencies and hence might not be stable, assert
VCO_SEL low to divide the VCO frequency by 2. This maintains
the desired output relationships but provides an enhanced PLL
lock range.
Table 2. Frequency Selection Table
VCO_SEL
0
0
0
0
1
1
1
1
SELA1
0
0
1
1
0
0
1
1
SELA0
0
1
0
1
0
1
0
1
QA
VCO/8
VCO/12
VCO/16
VCO/24
VCO/4
VCO/6
VCO/8
VCO/12
SELB1
0
0
1
1
0
0
1
1
SELB0
0
1
0
1
0
1
0
1
QB
VCO/8
VCO/12
VCO/16
VCO/20
VCO/4
VCO/6
VCO/8
VCO/10
SELC1
0
0
1
1
0
0
1
1
SELC0
0
1
0
1
0
1
0
1
QC
VCO/4
VCO/8
VCO/12
VCO/16
VCO/2
VCO/4
VCO/6
VCO/8
The CY29972 is also capable of providing inverted output clocks.
When INV_CLK is asserted HIGH, QC2 and QC3 output clocks
are inverted. These clocks could be used as feedback outputs to
the CY29972 or a second PLL device to generate early or late
clocks for a specific design. This inversion does not affect the
output to output skew.
Glitch-Free Output Frequency Transitions
Customarily, when output buffers have their internal counters
changed “on the fly,” their output clock periods will:
1. contain short or “runt” clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the old
or new frequencies to which the cycles are being transitioned.
2. contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old or
new frequencies to which the cycles are being transitioned.
This device specifically includes logic to guarantee that runt and
stretched clock pulses do not occur if the device logic levels of
any or all of the following pins changed “on the fly” while it is
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