HEF4093B
Quad 2-input NAND Schmitt trigger
Rev. 8 — 21 November 2011
Product data sheet
1. General description
The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit.
The gate switches at different points for positive-going and negative-going signals. The
difference between the positive voltage (V
T+
) and the negative voltage (V
T
) is defined as
hysteresis voltage (V
H
).
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Schmitt trigger input discrimination
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from40
C
to +85
C
and
40 C
to +125
C
Complies with JEDEC standard JESD 13-B
3. Applications
Wave and pulse shapers
Astable multivibrators
Monostable multivibrators
4. Ordering information
Table 1.
Ordering information
All types operate from
40 C
to +125
C
Type number
HEF4093BP
HEF4093BT
Package
Name
DIP14
SO14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width 3.9 mm
Version
SOT27-1
SOT108-1
NXP Semiconductors
HEF4093B
Quad 2-input NAND Schmitt trigger
5. Functional diagram
1A
1
3
1Y
1B
2
2A
5
4
2Y
nA
nY
10
nB
3Y
001aag105
2B
6
3A
8
3B
9
4A
12
11
4Y
4B
13
001aag104
Fig 1.
Functional diagram
Fig 2.
Logic diagram (one gate)
6. Pinning information
6.1 Pinning
1A
1B
1Y
2Y
2A
2B
V
SS
1
2
3
4
5
6
7
001aag106
14 V
DD
13 4B
12 4A
HEF4093B
11 4Y
10 3Y
9
8
3B
3A
Fig 3.
Pin configuration
HEF4093B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
2 of 15
NXP Semiconductors
HEF4093B
Quad 2-input NAND Schmitt trigger
6.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
V
DD
V
SS
Pin description
Pin
1, 5, 8, 12
2, 6, 9, 13
3, 4, 10, 11
14
7
Description
input
input
output
supply voltage
ground (0 V)
7. Functional description
Table 3.
Input
nA
L
L
H
H
[1]
Function table
[1]
Output
nB
L
H
L
H
nY
H
H
H
L
H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
T
amb
=
40 C
to +125
C
DIP14
SO14
P
[1]
[2]
[1]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
Min
0.5
-
0.5
-
-
-
65
40
-
-
-
Max
+18
10
V
DD
+ 0.5
10
10
50
+150
+125
750
500
100
Unit
V
mA
V
mA
mA
mA
C
C
mW
mW
mW
power dissipation
per output
For DIP14 packages: above T
amb
= 70
C,
P
tot
derates linearly with 12 mW/K.
For SO14 packages: above T
amb
= 70
C,
P
tot
derates linearly with 8 mW/K.
HEF4093B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
3 of 15
NXP Semiconductors
HEF4093B
Quad 2-input NAND Schmitt trigger
9. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
in free air
Conditions
Min
3
0
40
Max
15
V
DD
+125
Unit
V
V
C
10. Static characteristics
Table 6.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter
V
OH
HIGH-level
output voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
OL
LOW-level
output voltage
I
O
< 1
A
5V
10 V
15 V
I
OH
HIGH-level
output current
V
O
= 2.5 V
V
O
= 4.6 V
V
O
= 9.5 V
V
O
= 13.5 V
I
OL
LOW-level
output current
V
O
= 0.4 V
V
O
= 0.5 V
V
O
= 1.5 V
I
I
I
DD
input leakage
current
supply current
5V
5V
10 V
15 V
5V
10 V
15 V
15 V
5V
all valid input
combinations; 10 V
I
O
= 0 A
15 V
T
amb
=
40 C
T
amb
= +25
C
T
amb
= +85
C
T
amb
= +125
C
Unit
Min
4.95
9.95
14.95
-
-
-
-
-
-
-
0.64
1.6
4.2
-
-
-
-
-
Max
-
-
-
0.05
0.05
0.05
1.7
0.64
1.6
4.2
-
-
-
0.1
0.25
0.5
1.0
-
Min
4.95
9.95
14.95
-
-
-
-
-
-
-
0.5
1.3
3.4
-
-
-
-
-
Max
-
-
-
0.05
0.05
0.05
1.4
0.5
1.3
3.4
-
-
-
0.1
0.25
0.5
1.0
7.5
Min
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
-
-
-
0.05
0.05
0.05
1.1
0.36
0.9
2.4
-
-
-
1.0
7.5
15.0
30.0
-
Min
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
-
-
-
0.05
0.05
0.05
1.1
0.36
0.9
2.4
-
-
-
1.0
7.5
15.0
30.0
-
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
A
A
A
A
pF
C
I
input
capacitance
HEF4093B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
4 of 15
NXP Semiconductors
HEF4093B
Quad 2-input NAND Schmitt trigger
11. Dynamic characteristics
Table 7.
Dynamic characteristics
T
amb
= 25
C;
C
L
= 50 pF; t
r
= t
f
20 ns; wave forms see
Figure 4;
test circuit see
Figure 5;
unless otherwise specified.
Symbol Parameter
t
PHL
HIGH to LOW
propagation delay
Conditions
nA or nB to nY
V
DD
5V
10 V
15 V
t
PLH
LOW to HIGH
propagation delay
nA or nB to nY
5V
10 V
15 V
t
THL
HIGH to LOW output
transition time
nY to LOW
5V
10 V
15 V
t
TLH
LOW to HIGH output
transition time
nA or nB to
HIGH
5V
10 V
15 V
[1]
Extrapolation formula
[1]
63 ns + (0.55 ns/pF)C
L
29 ns + (0.23 ns/pF)C
L
22 ns + (0.16 ns/pF)C
L
58 ns + (0.55 ns/pF)C
L
29 ns + (0.23 ns/pF)C
L
22 ns + (0.16 ns/pF)C
L
10 ns + (1.00 ns/pF)C
L
9 ns + (0.42 ns/pF)C
L
6 ns + (0.28 ns/pF)C
L
10 ns + (1.00 ns/pF)C
L
9 ns + (0.42 ns/pF)C
L
6 ns + (0.28 ns/pF)C
L
Min
-
-
-
-
-
-
-
-
-
-
-
-
Typ
90
40
30
85
40
30
60
30
20
60
30
20
Max
185
80
60
170
80
60
120
60
40
120
60
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (C
L
in pF).
Table 8.
Dynamic power dissipation
V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter
P
D
dynamic power
dissipation
V
DD
5V
10 V
15 V
Typical formula
P
D
= 1300
f
i
+
(f
o
C
L
)
V
DD2
(W)
P
D
= 6400
f
i
+
(f
o
C
L
)
V
DD2
(W)
P
D
= 18700
f
i
+
(f
o
C
L
)
V
DD2
(W)
where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
(f
o
C
L
) = sum of the outputs;
V
DD
= supply voltage in V.
HEF4093B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
5 of 15
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