IMPORTANT NOTICE
Dear customer,
As from August 2
nd
2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●
Company name - NXP B.V.
is replaced with
ST-NXP Wireless.
Copyright
- the copyright notice at the bottom of each page “© NXP B.V. 200x. All
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
Web site
-
http://www.nxp.com
is replaced with
http://www.stnwireless.com
Contact information
- the list of sales offices previously obtained by sending
an email to
salesaddresses@nxp.com
, is now found at
http://www.stnwireless.com
under Contacts.
●
●
●
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
www.stnwireless.com
ISP1761
Hi-Speed Universal Serial Bus On-The-Go controller
Rev. 05 — 13 March 2008
Product data sheet
1. General description
The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)
Controller integrated with advanced NXP slave host controller and the NXP ISP1582
peripheral controller.
The Hi-Speed USB host controller and peripheral controller comply to
Ref. 1 “Universal
Serial Bus Specification Rev. 2.0”
and support data transfer speeds of up to 480 Mbit/s.
The Enhanced Host Controller Interface (EHCI) core implemented in the host controller is
adapted from
Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial
Bus Rev. 1.0”.
The OTG controller adheres to
Ref. 3 “On-The-Go Supplement to the USB
Specification Rev. 1.3”.
The ISP1761 has three USB ports. Port 1 can be configured to function as a downstream
port, an upstream port or an OTG port; ports 2 and 3 are always configured as
downstream ports. The OTG port can switch its role from host to peripheral, and
peripheral to host. The OTG port can become a host through the Host Negotiation
Protocol (HNP) as specified in the OTG supplement.
2. Features
I
Compliant with
Ref. 1 “Universal Serial Bus Specification Rev. 2.0”;
supporting data
transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
I
Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed)
peripheral support
I
Three USB ports that support three operational modes:
N
Mode 1: Port 1 is an OTG controller port, and ports 2 and 3 are host controller
ports
N
Mode 2: Ports 1, 2 and 3 are host controller ports
N
Mode 3: Port 1 is a peripheral controller port, and ports 2 and 3 are host controller
ports
I
Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
I
Multitasking support with virtual segmentation feature (up to four banks)
I
High-speed memory controller (variable latency and SRAM external interface)
I
Directly addressable memory architecture
I
Generic processor interface to most CPUs, such as Hitachi SH-3 and SH-4, NXP XA,
Intel StrongARM, NEC and Toshiba MIPS, Freescale DragonBall and PowerPC
Reduced Instruction Set Computer (RISC) processors
I
Configurable 32-bit and 16-bit external memory data bus
I
Supports Programmed I/O (PIO) and Direct Memory Access (DMA)
I
Slave DMA implementation on CPU interface to reduce the host system’s CPU load
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
I
Separate IRQ, DREQ and DACK lines for the host controller and the peripheral
controller
I
Integrated multi-configuration FIFO
I
Double-buffering scheme increases throughput and facilitates real-time data transfer
I
Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low EMI
I
Tolerant I/O for low voltage CPU interface (1.65 V to 3.3 V)
I
3.3 V-to-5.0 V external power supply input
I
Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for
low-power core)
I
Internal power-on reset or low-voltage reset and block-dedicated software reset
I
Supports suspend and remote wake-up
I
Built-in overcurrent circuitry (analog overcurrent protection)
I
Hybrid-power mode: V
CC(5V0)
(can be switched off), V
CC(I/O)
(permanent)
I
Target total current consumption:
N
Normal operation; one port in high-speed active: I
CC
< 100 mA when the internal
charge pump is not used
N
Suspend mode: I
CC(susp)
< 150
µA
at ambient temperature of +25
°C
I
Available in LQFP128 and TFBGA128 packages
I
Host controller-specific features
N
High performance USB host with integrated Hi-Speed USB transceivers; supports
high-speed, full-speed and low-speed
N
EHCI core is adapted from
Ref. 2 “Enhanced Host Controller Interface
Specification for Universal Serial Bus Rev. 1.0”
N
Configurable power management
N
Integrated TT for Original USB peripheral support on all three ports
N
Integrated 64 kB high-speed memory (internally organized as 8 k
×
64 bit)
N
Additional 2.5 kB separate memory for TT
N
Individual or global overcurrent protection with built-in sense circuits
N
Built-in overcurrent circuitry (digital or analog overcurrent protection)
I
OTG controller-specific features
N
OTG transceiver: fully integrated; adheres to
Ref. 3 “On-The-Go Supplement to the
USB Specification Rev. 1.3”
N
Supports HNP and SRP for OTG dual-role devices
N
HNP: status and control registers for software implementation
N
SRP: status and control registers for software implementation
N
Programmable timers with high resolution (0.01 ms to 80 ms) for HNP and SRP
N
Supports external source of V
BUS
I
Peripheral controller-specific features
N
High-performance USB peripheral controller with integrated Serial Interface Engine
(SIE), FIFO memory and transceiver
N
Complies with
Ref. 1 “Universal Serial Bus Specification Rev. 2.0”
and most device
class specifications
N
Supports auto Hi-Speed USB mode discovery and Original USB fallback
capabilities
N
Supports high-speed and full-speed on the peripheral controller
N
Bus-powered or self-powered capability with suspend mode
ISP1761_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
2 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
N
Slave DMA, fully autonomous and supports multiple configurations
N
Seven IN endpoints, seven OUT endpoints and one fixed control IN and OUT
endpoint
N
Integrated 8 kB memory
N
Software-controllable connection to the USB bus, SoftConnect
3. Applications
The ISP1761 can be used to implement a dual-role USB device in any application, USB
host or USB peripheral, depending on the cable connection. If the dual-role device is
connected to a typical USB peripheral, it behaves like a typical USB host. The dual-role
device can also be connected to a PC or any other USB host and behave like a typical
USB peripheral.
3.1 Host/peripheral roles
I
Mobile phone to/from:
N
Mobile phone: exchange contact information
N
Digital still camera: e-mail pictures or upload pictures to the web
N
MP3 player: upload/download/broadcast music
N
Mass storage: upload/download files
N
Scanner: scan business cards
I
Digital still camera to/from:
N
Digital still camera: exchange pictures
N
Mobile phone: e-mail pictures, upload pictures to the web
N
Printer: print pictures
N
Mass storage: store pictures
I
Printer to/from:
N
Digital still camera: print pictures
N
Scanner: print scanned image
N
Mass storage: print files stored in a device
I
MP3 player to/from:
N
MP3 player: exchange songs
N
Mass storage: upload/download songs
I
Oscilloscope to/from:
N
Printer: print screen image
I
Personal digital assistant to/from:
N
Personal digital assistant: exchange files
N
Printer: print files
N
Mobile phone: upload/download files
N
MP3 player: upload/download songs
N
Scanner: scan pictures
N
Mass storage: upload/download files
N
Global Positioning System (GPS): obtain directions, mapping information
N
Digital still camera: upload pictures
N
Oscilloscope: configure oscilloscope
ISP1761_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
3 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
4. Ordering information
Table 1.
Ordering information
Package
Name
ISP1761BE
ISP1761ET
LQFP128
Description
plastic low profile quad flat package; 128 leads; body 14
×
20
×
1.4 mm
Version
SOT425-1
SOT857-1
Type number
TFBGA128 plastic thin fine-pitch ball grid array package; 128 balls; body 9
×
9
×
0.8 mm
ISP1761_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
4 of 163
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