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SN74CBT6800DGVR

Description
CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, TVSOP-24
Categorylogic    logic   
File Size796KB，8 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
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SN74CBT6800DGVR Overview

CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, TVSOP-24

SN74CBT6800DGVR Parametric

Parameter NameAttribute value
MakerRochester Electronics
Parts packaging codeSOIC
package instructionTSSOP,
Contacts24
Reach Compliance Codeunknown
seriesCBT/FST/QS/5C/B
JESD-30 codeR-PDSO-G24
length5 mm
Logic integrated circuit typeBUS DRIVER
Number of digits10
Number of functions1
Number of ports2
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)0.35 ns
Certification statusCOMMERCIAL
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4 V
Nominal supply voltage (Vsup)5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.4 mm
Terminal locationDUAL
width4.4 mm

SN74CBT6800DGVR Preview

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SN74CBT6800
10-BIT FET BUS SWITCH
WITH PRECHARGED OUTPUTS FOR LIVE INSERTION
SCDS005J – MARCH 1993 – REVISED DECEMBER 1998
D
D
D
D
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
Outputs Are Precharged by Bias Voltage to
Minimize Signal Distortion During Live
Insertion
Package Options Include Plastic Shrink
Small-Outline (DB, DBQ), Small-Outline
(DW), and Thin Shrink Small-Outline (PW)
Packages
DB, DBQ, DW, OR PW PACKAGE
(TOP VIEW)
description
The SN74CBT6800 provides ten bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
bidirectional connections to be made while adding
near-zero propagation delay. The device also
precharges the B port to a user-selectable bias
voltage (BIASV) to minimize live-insertion noise.
ON
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
BIASV
The SN74CBT6800 is organized as one 10-bit switch with a single enable (ON) input. When ON is low, the
switch is on and port A is connected to port B. When ON is high, the switch between port A and port B is open
and the B port is precharged to BIASV through the equivalent of a 10-kΩ resistor.
The SN74CBT6800 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
ON
L
H
B1–B10
A1–A10
BIASV
FUNCTION
Connect
Precharge
logic diagram (positive logic)
13
BIASV
2
A1
23
B1
11
A10
14
B10
1
ON
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SN74CBT6800
10-BIT FET BUS SWITCH
WITH PRECHARGED OUTPUTS FOR LIVE INSERTION
SCDS005J – MARCH 1993 – REVISED DECEMBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Bias voltage range, BIASV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance,
θ
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN
VCC
BIASV
VIH
VIL
Supply voltage
Supply voltage
High-level control input voltage
Low-level control input voltage
4
1.3
2
0.8
MAX
5.5
VCC
UNIT
V
V
V
V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
II
IO
ICC
∆I
CC§
Ci
Co(OFF)
Control inputs
Control inputs
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 3.6 V,
VI = 3 V or 0
VO = 3 V or 0,
VCC = 4 V,
TYP at VCC = 4 V
ron¶
VCC = 4.5 V
TEST CONDITIONS
II = –18 mA
VI = 5.5 V or GND
BIASV = 2.4 V,
IO = 0,
One input at 2.7 V,
Switch off
VI = 2.4 V,
VI = 0
II = 15 mA
II = 64 mA
II = 30 mA
VO= 0
VI = VCC or GND
Other inputs at VCC or GND
3.5
4.5
14
5
5
20
7
7
Ω
0.25
50
2.5
MIN
TYP‡
MAX
–1.2
±5
UNIT
V
µA
mA
µA
mA
pF
pF
VI = 2.4 V,
II = 15 mA
10
15
‡ All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN74CBT6800
10-BIT FET BUS SWITCH
WITH PRECHARGED OUTPUTS FOR LIVE INSERTION
SCDS005J – MARCH 1993 – REVISED DECEMBER 1998
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd†
tPZH
tPZL
tPHZ
tPLZ
BIASV = GND
BIASV = 3 V
BIASV = GND
BIASV = 3 V
ON
TEST
CONDITIONS
FROM
(INPUT)
A or B
TO
(OUTPUT)
B or A
A or B
VCC = 4 V
MIN
MAX
0.35
9.1
9.6
5.9
6.4
3.1
3.6
2.7
3
VCC = 5 V
±
0.5 V
MIN
MAX
0.25
8.1
8.6
6.1
7.3
ns
ns
UNIT
ON
A or B
ns
† The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
CL = 50 pF
(see Note A)
500
Ω
S1
Open
GND
500
Ω
Output
Control
(low-level
enabling)
tPZL
Output
Waveform 1
S1 at 7 V
(see Note B)
tPZH
VOH
Output
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7V
Open
3V
1.5 V
1.5 V
0V
tPLZ
3.5 V
1.5 V
tPHZ
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOL + 0.3 V
VOL
LOAD CIRCUIT
3V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
Ω,
tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright
©
2000, Texas Instruments Incorporated
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SN74CBT6800DGVR Related Products

SN74CBT6800DGVR SN74CBT6800DBQR SN74CBT6800DW SN74CBT6800DWR SN74CBT6800DBR SN74CBT6800DBLE SN74CBT6800PWR
Description CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, TVSOP-24 CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, SSOP-24 CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24 CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24 CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, SSOP-24 CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, SSOP-24 CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, TSSOP-24
Maker Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics
Parts packaging code SOIC SSOP SOIC SOIC SSOP SSOP TSSOP
package instruction TSSOP, SSOP-24 PLASTIC, SO-24 PLASTIC, SO-24 SSOP-24 SSOP-24 TSSOP-24
Contacts 24 24 24 24 24 24 24
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown
series CBT/FST/QS/5C/B CBT/FST/QS/5C/B CBT/FST/QS/5C/B CBT/FST/QS/5C/B CBT/FST/QS/5C/B CBT/FST/QS/5C/B CBT/FST/QS/5C/B
JESD-30 code R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24
length 5 mm 8.6614 mm 15.4 mm 15.4 mm 8.2 mm 8.2 mm 7.8 mm
Logic integrated circuit type BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER
Number of digits 10 10 10 10 10 10 10
Number of functions 1 1 1 1 1 1 1
Number of ports 2 2 2 2 2 2 2
Number of terminals 24 24 24 24 24 24 24
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Output polarity TRUE TRUE TRUE TRUE TRUE TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP SSOP SOP SOP SSOP SSOP TSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd) 0.35 ns 0.35 ns 0.35 ns 0.35 ns 0.35 ns 0.35 ns 0.35 ns
Certification status COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Maximum seat height 1.2 mm 1.75 mm 2.65 mm 2.65 mm 2 mm 2 mm 1.2 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4 V 4 V 4 V 4 V 4 V 4 V 4 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES YES YES YES YES YES YES
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.4 mm 0.635 mm 1.27 mm 1.27 mm 0.65 mm 0.65 mm 0.65 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL DUAL
width 4.4 mm 3.9116 mm 7.5 mm 7.5 mm 5.3 mm 5.3 mm 4.4 mm
Is it lead-free? - Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead
JESD-609 code - e0 e0 e0 e0 e0 e4
Humidity sensitivity level - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 1
Peak Reflow Temperature (Celsius) - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 250
Terminal surface - TIN LEAD TIN LEAD TIN LEAD TIN LEAD TIN LEAD NICKEL PALLADIUM GOLD
Maximum time at peak reflow temperature - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED

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