8432CY-51LFT datasheet, PDF - EEWORLD Datasheet

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8432CY-51LFT: DescriptionTQFP-32, Reel; CategoryThe embedded processor and controller Microcontrollers and processors; File Size427KB，22 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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8432CY-51LFT Overview

TQFP-32, Reel

8432CY-51LFT Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	LQFP-32
Contacts	32
Manufacturer packaging code	PRG32
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	S-PQFP-G32
JESD-609 code	e3
length	7 mm
Humidity sensitivity level	3
Number of terminals	32
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	700 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	50 MHz
Maximum seat height	1.6 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

8432CY-51LFT Preview

700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL

LVPECL FREQUENCY SYNTHESIZER

ICS8432-51

ENERAL

ESCRIPTION

The ICS8432-51 is a general purpose, dual output Crystal-to-

3.3V Differential LVPECL High Frequency Synthesizer. The

ICS8432-51 has a selectable REF_CLK or crystal input. The

VCO operates at a frequency range of 250MHz to 700MHz. The

VCO frequency is programmed in steps equal to the value of

the input reference or crystal frequency. The VCO and output

frequency can be programmed using the serial or parallel inter-

face to the configuration logic. The low phase noise character-

istics of the ICS8432-51 make it an ideal clock source for Giga-

bit Ethernet, Fibre Channel 1 and 2, and Infiniband applica-

tions.

EATURES

•

Dual differential 3.3V LVPECL outputs

•

Selectable crystal oscillator interface or

LVCMOS/LVTTL REF_CLK

•

Output frequency range: 31.25MHz to 700MHz

•

Crystal input frequency range: 12MHz to 25MHz

•

VCO range: 250MHz to 700MHz

•

Parallel or serial interface for programming counter and

output dividers

•

RMS period jitter: 3.5ps (maximum)

•

Cycle-to-cycle jitter: 25ps (maximum)

•

3.3V supply voltage

•

0°C to 70°C ambient operating temperature

•

Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

•

Replaces the ICS8432-01

LOCK

IAGRAM

SSIGNMENT

VCO_SEL

nP_LOAD

XTAL_IN

VCO_SEL

XTAL_SEL

REF_CLK

XTAL1

OSC

XTAL2

32 31 30 29 28 27 26 25

XTAL_OUT

REF_CLK

XTAL_SEL

CCA

S_LOAD

S_DATA

S_CLOCK

ICS8432-51

PLL

PHASE DETECTOR

÷1

÷2

÷4

÷8

9 10 11 12 13 14 15 16

TEST

FOUT1

nFOUT1

CCO

FOUT0

nFOUT0

VCO

FOUT0

nFOUT0

FOUT1

nFOUT1

S_LOAD

S_DATA

S_CLOCK

nP_LOAD

M0:M8

N0:N1

CONFIGURATION

INTERFACE

LOGIC

TEST

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

32-Lead VFQFN

5mm x 5mm x 0.925mm package body

K Package

Top View

IDT

™

/ ICS

™

3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8432CY-51 REVISION F NOVEMBER 13, 2012

ICS8432-51

700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

UNCTIONAL

ESCRIPTION

NOTE: The functional description that follows describes opera-

tion using a 25MHz crystal. Valid PLL loop divider values for dif-

ferent crystal or input frequencies are defined in the Input

Frequency Characteristics, Table 5, NOTE 1.

The ICS8432-51 features a fully integrated PLL and therefore,

requires no external components for setting the loop bandwidth.

A fundamental crystal is used as the input to the on-chip oscilla-

tor. The output of the oscillator is fed into the phase detector.

A 25MHz crystal provides a 25MHz phase detector reference

frequency. The VCO of the PLL operates over a range of 250MHz

to 700MHz. The output of the M divider is also applied to the

phase detector.

The phase detector and the M divider force the VCO output fre-

quency to be M times the reference frequency by adjusting the

VCO control voltage. Note that for some values of M (either too high

or too low), the PLL will not achieve lock. The output of the VCO is

scaled by a divider prior to being sent to each of the LVPECL output

buffers. The divider provides a 50% output duty cycle.

The programmable features of the ICS8432-51 support two in-

put modes to program the M divider and N output divider. The

two input operational modes are parallel and serial.

Figure 1

shows

the timing diagram for each mode. In parallel mode, the nP_LOAD

input is initially LOW. The data on inputs M0 through M8 and N0

and N1 is passed directly to the M divider and N output divider.

On the LOW-to-HIGH transition of the nP_LOAD input, the data

is latched and the M divider remains loaded until the next LOW

transition on nP_LOAD or until a serial event occurs. As a result,

the M and N bits can be hardwired to set the M divider and

N output divider to a specific default state that will automatically

occur during power-up. The TEST output is LOW when operating

in the parallel input mode. The relationship between the VCO

frequency, the crystal frequency and the M divider is defined as

follows:

fVCO = fxtal x M

The M value and the required values of M0 through M8 are shown

in Table 3B, Programmable VCO Frequency Function Table.

Valid M values for which the PLL will achieve lock for a 25MHz

reference are defined as 10

≤

28. The frequency out is de-

fined as follows:

FOUT

fVCO = fxtal x M

Serial operation occurs when nP_LOAD is HIGH and S_LOAD is

LOW. The shift register is loaded by sampling the S_DATA bits

with the rising edge of S_CLOCK. The contents of the shift reg-ister

are loaded into the M divider and N output divider when S_LOAD

transitions from LOW-to-HIGH. The M divide and N output divide

values are latched on the HIGH-to-LOW transition of S_LOAD. If

S_LOAD is held HIGH, data at the S_DATA input is passed directly

to the M divider and N output divider on each ris-ing edge of

S_CLOCK. The serial mode can be used to program the M and N

bits and test bits T1 and T0. The internal registers T0 and T1 deter-

mine the state of the TEST output as follows:

TEST Output

LOW

S_Data, Shift Register Input

Output of M divider

CMOS Fout

ERIAL

OADING

S_CLOCK

S_DATA

*NULL

S_LOAD

nP_LOAD

ARALLEL

OADING

M0:M8, N0:N1

M, N

nP_LOAD

S_LOAD

Time

IGURE

1. P

ARALLEL

& S

ERIAL

OAD

PERATIONS

*NOTE:

The NULL timing slot must be observed.

IDT

™

/ ICS

™

3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8432CY-51 REVISION F NOVEMBER 13, 2012

ICS8432-51

700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

ABLE

1. P

ESCRIPTIONS

Number

2, 3, 4,

28, 29,

30, 31, 32

5, 6

8, 16

11, 12

14, 15

Name

M6, M7, M8,

M0, M1,

M2, M3, M4

N0, N1

TEST

FOUT1, nFOUT1

CCO

FOUT0, nFOUT0

Input

Unused

Power

Output

Power

Output

Power

Output

Type

Pullup

M divider inputs. Data latched on LOW-to-HIGH transition

Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels.

Pulldown

Determines output divider value as defined in Table 3C,

Function Table. LVCMOS / LVTTL interface levels.

No connect.

Negative supply pins.

Test output which is ACTIVE in the serial mode of operation. Output

driven LOW in parallel mode. LVCMOS / LVTTL interface levels.

Core supply pin.

Differential output for the synthesizer. 3.3V LVPECL interface levels.

Output supply pin.

Differential output for the synthesizer. 3.3V LVPECL interface levels.

Active High Master Reset. When logic HIGH, the internal dividers

are reset causing the true outputs FOUTx to go low and the

inverted outputs nFOUTx to go high. When logic LOW, the internal

dividers and the outputs are enabled. Assertion of MR does not

effect loaded M, N, and T values. LVCMOS / LVTTL interface levels.

Clocks in serial data present at S_DATA input into the shift register

on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.

Shift register serial input. Data sampled on the rising edge of

S_CLOCK. LVCMOS / LVTTL interface levels.

Controls transition of data from shift register into the dividers.

LVCMOS / LVTTL interface levels.

Analog supply pin.

Pullup

Selects between crystal or test inputs as the PLL reference source.

Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.

LVCMOS / LVTTL interface levels.

Description

Input

Pulldown

24,

S_CLOCK

S_DATA

S_LOAD

CCA

XTAL_SEL

REF_CLK

XTAL_OUT,

XTAL_IN

nP_LOAD

VCO_SEL

Input

Power

Input

Pulldown

Pulldown Referenc clock input. LVCMOS / LVTTL interface levels.

Crystal oscillator interface. XTAL_IN is the input.

XTAL_OUT is the output.

Parallel load input. Determines when data present at M8:M0 is

Pulldown loaded into M divider, and when data present at N1:N0 sets the

N output divider value. LVCMOS / LVTTL interface levels.

Determines whether synthesizer is in PLL or bypass mode.

Pullup

LVCMOS / LVTTL interface levels.

NOTE:

Pullup

and

Pulldown

refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

ABLE

2. P

HARACTERISTICS

Symbol

PULLUP

PULLDOWN

Parameter

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

Test Conditions

Minimum

Typical

Maximum

Units

k

IDT

™

/ ICS

™

3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8432CY-51 REVISION F NOVEMBER 13, 2012

ICS8432-51

700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

ABLE

3A. P

ARALLEL

AND

ERIAL

ODE

UNCTION

ABLE

Inputs

Conditions

S_CLOCK



S_DATA

Data

Reset. Forces outputs LOW.

Data on M and N inputs passed directly to the M

divider and N output divider. TEST output forced LOW.

Data is latched into input registers and remains loaded

until next LOW transition or until a serial event occurs.

Serial input mode. Shift register is loaded with data on

S_DATA on each rising edge of S_CLOCK.

Contents of the shift register are passed to the

M divider and N output divider.

M divider and N output divider values are latched.

Parallel or serial input do not affect shift registers.

S_DATA passed directly to M divider as it is clocked.





nP_LOAD



Data

S_LOAD

NOTE: L = LOW

H = HIGH

X = Don't care



= Rising edge transition



= Falling edge transition

ABLE

3B. P

ROGRAMMABLE

VCO F

REQUENCY

UNCTION

ABLE

VCO Frequency

(MHz)

250

275

•

650

675

M Divide

•

256

•

128

•

700

NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency

of 25MHz.

ABLE

3C. P

ROGRAMMABLE

UTPUT

IVIDER

UNCTION

ABLE

Inputs

N Divider Value

Output Frequency (MHz)

Minimum

250

125

62.5

31.25

Maximum

700

350

175

87.5

IDT

™

/ ICS

™

3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8432CY-51 REVISION F NOVEMBER 13, 2012

ICS8432-51

700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

BSOLUTE

AXIMUM

ATINGS

Supply Voltage, V

Inputs, V

Outputs, I

Continuous Current

Surge Current

Package Thermal Impedance,

32 Lead LQFP

32 Lead VFQFN

Storage Temperature, T

STG

4.6V

-0.5V to V

+ 0.5 V

50mA

100mA

47.9°C/W (0 lfpm)

41.07°C/W (0 lfpm)

-65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional op-

eration of product at these conditions or any conditions beyond

those listed in the

DC Characteristics

AC Characteristics

is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

ABLE

4A. P

OWER

UPPLY

DC C

HARACTERISTICS

= V

CCO

= 3.3V±5%, T

= 0°C

70°C

Symbol

CCA

CCO

CCA

Parameter

Core Supply Voltage

Analog Supply Voltage

Output Supply Voltage

Power Supply Current

Analog Supply Current

Test Conditions

Minimum

3.135

–0.15

3.135

Typical

3.3

Maximum

3.465

135

Units

ABLE

4B. LVCMOS / LVTTL DC C

HARACTERISTICS

= V

CCO

= 3.3V±5%, T

= 0°C

70°C

Symbol

Parameter

Input

High Voltage

VCO_SEL, XTAL_SEL, MR,

S_LOAD, nP_LOAD, N0:N1,

S_DATA, S_CLOCK, M0:M8

REF_CLK

VCO_SEL, XTAL_SEL, MR,

S_LOAD, nP_LOAD, N0:N1,

S_DATA, S_CLOCK, M0:M8

REF_CLK

M0-M4, M6-M8, N0, N1, MR,

S_CLOCK, REF_CLK,

S_DATA, S_LOAD, nP_LOAD

M5, XTAL_SEL, VCO_SEL

M0-M4, M6-M8, N0, N1, MR,

S_CLOCK, REF_CLK,

S_DATA, S_LOAD, nP_LOAD

M5, XTAL_SEL, VCO_SEL

Output

High Voltage

Output

Low Voltage

TEST; NOTE 1

Test Conditions

Minimum

-0.3

= V

= 3.465V

= V

= 3.465V

= 3.465V,

= 0V

= 3.465V,

= 0V

-5

Typical

Maximum

+ 0.3

0.8

1.3

150

Units

µA

Input

Low Voltage

Input

High Current

Input

Low Current

-150

2.6

0.5

µA

NOTE 1: Outputs terminated with 50Ω to V

CCO

/2.

IDT

™

/ ICS

™

3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8432CY-51 REVISION F NOVEMBER 13, 2012

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8432CY-51LFT Related Products

	8432CY-51LFT	8432CK-51LF	8432CK-51LFT
Description	TQFP-32, Reel	VFQFPN-32, Tray	VFQFPN-32, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TQFP	VFQFPN	VFQFPN
package instruction	LQFP-32	VFQFN-32	VFQFN-32
Contacts	32	32	32
Manufacturer packaging code	PRG32	NLG32P1	NLG32P1
Reach Compliance Code	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99
JESD-30 code	S-PQFP-G32	S-XQCC-N32	S-XQCC-N32
JESD-609 code	e3	e3	e3
length	7 mm	5 mm	5 mm
Humidity sensitivity level	3	3	3
Number of terminals	32	32	32
Maximum operating temperature	70 °C	70 °C	70 °C
Maximum output clock frequency	700 MHz	700 MHz	700 MHz
Package body material	PLASTIC/EPOXY	UNSPECIFIED	UNSPECIFIED
encapsulated code	LQFP	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260	260
Master clock/crystal nominal frequency	50 MHz	50 MHz	50 MHz
Maximum seat height	1.6 mm	1 mm	1 mm
Maximum supply voltage	3.465 V	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	NO LEAD	NO LEAD
Terminal pitch	0.8 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	7 mm	5 mm	5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER

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