DISCRETE SEMICONDUCTORS
DATA SHEET
PHP1035
P-channel enhancement mode
MOS transistor
Preliminary specification
File under Discrete Semiconductors, SC13b
1998 Feb 18
Philips Semiconductors
Preliminary specification
P-channel enhancement mode
MOS transistor
FEATURES
•
Very low R
DSon
•
High-speed switching
•
No secondary breakdown
•
Direct interface to C-MOS, TTL, etc.
APPLICATIONS
•
Power management
•
DC-DC converters
•
General purpose switch.
DESCRIPTION
P-channel enhancement mode MOS transistor in an 8-pin
SOT96-1 (SO8) SMD plastic package.
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
1
Top view
4
handbook, halfpage
8
PHP1035
PINNING - SOT96-1 (SO8)
PIN
1
2
3
4
5
6
7
8
SYMBOL
s
s
s
g
d
d
d
d
source
source
source
gate
drain
drain
drain
drain
DESCRIPTION
5
d
g
s
MAM398
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
V
DS
V
SD
V
GSO
V
GSth
I
D
R
DSon
P
tot
PARAMETER
drain-source voltage (DC)
source-drain diode forward voltage
gate-source voltage (DC)
gate-source threshold voltage
drain current (DC)
drain-source on-state resistance
total power dissipation
I
S
=
−1.25
A; V
GD
= 0
open drain
I
D
=
−1
mA; V
DS
= V
GS
T
s
= 80
°C
I
D
=
−4
A; V
GS
=
−10
V
T
s
= 80
°C
CONDITIONS
−
−
−
−1
−
−
−
MIN.
MAX.
−30
−1.3
±20
−
−8
35
4
V
V
V
V
A
mΩ
W
UNIT
1998 Feb 18
2
Philips Semiconductors
Preliminary specification
P-channel enhancement mode
MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DS
V
GSO
I
D
I
DM
P
tot
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
open drain
T
s
= 80
°C;
note 1
note 2
T
s
= 80
°C
T
amb
= 25
°C;
note 3
T
amb
= 25
°C;
note 4
T
stg
T
j
I
S
I
SM
Notes
1. T
s
is the temperature at the soldering point of the drain lead.
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Device mounted on a printed-circuit board with a R
th a-tp
(ambient to tie-point) of 27.5 K/W.
4. Device mounted on a printed-circuit board with a R
th a-tp
(ambient to tie-point) of 90 K/W.
THERMAL CHARACTERISTICS
SYMBOL
R
th j-s
PARAMETER
thermal resistance from junction to soldering point
VALUE
17.5
storage temperature
operating junction temperature
T
s
= 80
°C
note 2
CONDITIONS
−
−
−
−
−
−
−
−55
−55
−
−
MIN.
PHP1035
MAX.
−30
±20
−8
−32
4
2.78
1.16
+150
+150
−3
−12
V
V
A
A
UNIT
W
W
W
°C
°C
Source-drain diode
source current (DC)
peak pulsed source current
A
A
UNIT
K/W
1998 Feb 18
3
Philips Semiconductors
Preliminary specification
P-channel enhancement mode
MOS transistor
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
V
(BR)DSS
V
GSth
I
DSS
I
GSS
R
DSon
C
iss
C
oss
C
rss
Q
G
Q
GS
Q
GD
PARAMETER
drain-source breakdown voltage
gate-source threshold voltage
drain-source leakage current
gate leakage current
drain-source on-state resistance
input capacitance
output capacitance
reverse transfer capacitance
total gate charge
gate-source charge
gate-drain charge
CONDITIONS
V
GS
= 0; I
D
=
−10 µA
V
GS
= V
DS
; I
D
=
−1
mA
V
GS
= 0; V
DS
=
−24
V
V
GS
=
±20
V; V
DS
= 0
V
GS
=
−4.5
V; I
D
= 2 A
V
GS
=
−10
V; I
D
=
−4
A
V
GS
= 0; V
DS
=
−24
V; f = 1 MHz
V
GS
= 0; V
DS
=
−24
V; f = 1 MHz
V
GS
= 0; V
DS
=
−24
V; f = 1 MHz
V
GS
=
−10
V; V
DD
=
−15
V;
I
D
=
−4
A; T
amb
= 25
°C
V
DD
=
−15
V; I
D
=
−4
A;
T
amb
= 25
°C
V
DD
=
−15
V; I
D
=
−4
A;
T
amb
= 25
°C
V
GS
= 0 to
−10
V; V
DD
=
−15
V;
I
D
=
−1
A; R
gen
= 6
Ω
V
GS
=
−10
to 0 V; V
DD
=
−15
V;
I
D
=
−1
A; R
gen
= 6
Ω
MIN.
−30
−1
−
−
−
−
−
−
−
−
−
−
TYP.
−
−
−
−
−
−
tbf
tbf
tbf
tbf
tbf
tbf
PHP1035
MAX.
−
−
−100
±100
50
35
−
−
−
−
−
−
UNIT
V
V
nA
nA
mΩ
mΩ
pF
pF
pF
pC
pC
nC
Switching times
t
d(on)
t
f
t
on
t
d(off)
t
r
t
off
V
SD
t
rr
turn-on delay time
fall time
turn-on switching time
turn-off delay time
rise time
turn-off switching time
V
GD
= 0; I
S
=
−1.25
A
I
S
=
−1.25
A; di/dt = 100 A/µs
−
−
−
−
−
−
−
−
tbf
tbf
tbf
tbf
tbf
tbf
−
tbf
−
−
−
−
−
−
−1.3
−
ns
ns
ns
ns
ns
ns
Source-drain diode
source-drain forward voltage
reverse recovery time
V
ns
1998 Feb 18
4
Philips Semiconductors
Preliminary specification
P-channel enhancement mode
MOS transistor
PACKAGE OUTLINE
SO8: plastic small outline package; 8 leads; body width 3.9 mm
PHP1035
SOT96-1
D
E
A
X
c
y
H
E
v
M
A
Z
8
5
Q
A
2
A
1
pin 1 index
θ
L
p
1
e
b
p
4
w
M
L
detail X
(A
3
)
A
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
mm
inches
A
max.
1.75
0.069
A
1
0.25
0.10
A
2
1.45
1.25
A
3
0.25
0.01
b
p
0.49
0.36
c
0.25
0.19
D
(1)
5.0
4.8
0.20
0.19
E
(2)
4.0
3.8
0.16
0.15
e
1.27
0.050
H
E
6.2
5.8
L
1.05
L
p
1.0
0.4
Q
0.7
0.6
v
0.25
0.01
w
0.25
0.01
y
0.1
0.004
Z
(1)
0.7
0.3
0.028
0.012
θ
0.010 0.057
0.004 0.049
0.019 0.0100
0.014 0.0075
0.244
0.039 0.028
0.041
0.228
0.016 0.024
8
0
o
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT96-1
REFERENCES
IEC
076E03S
JEDEC
MS-012AA
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-05-22
1998 Feb 18
5
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