80960JA/JF/JD/JS/JC/JT 3.3 V
Embedded 32-Bit Microprocessor
Datasheet
Product Features
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Code Compatible with all 80960Jx
Processors
High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Core Clock Rate is:
1x the Bus Clock for 80960JA/JF/JS
2x the Bus Clock for 80960JD/JC
3x the Bus Clock for 80960JT
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
Two-Way Set Associative Instruction
Cache
— 80960JA - 2 Kbyte
— 80960JF/JD - 4 Kbyte
— 80960JS/JC/JT - 16 Kbyte
— Programmable Cache-Locking
Mechanism
Direct Mapped Data Cache
— 80960JA - 1 Kbyte
— 80960JF/JD - 2 Kbyte
— 80960JS/JC/JT - 4 Kbyte
— Write Through Operation
On-Chip Stack Frame Cache
— Seven Register Sets May Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
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On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
3.3 V Supply Voltage
— 5 V Tolerant Inputs
— TTL Compatible Outputs
High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
High-Speed Interrupt Controller
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI#
— Up to 240 Vectors in Expanded Mode
Two On-Chip Timers
— Independent 32-Bit Counting
— Clock Prescaling by 1, 2, 4 or 8
— Internal Interrupt Sources
Halt Mode for Low Power
IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack
(PQFP)
— 196-Ball Mini Plastic Ball Grid Array
(MPBGA)
Order Number: 273159-006
August 2004
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
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Copyright © Intel Corporation, 2002, 2004
2
Datasheet
Contents
Contents
1.0
2.0
Introduction....................................................................................................................................
7
80960Jx Overview..........................................................................................................................
9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
3.0
3.1
3.2
80960 Processor Core ........................................................................................................ 10
Burst Bus ............................................................................................................................ 11
Timer Unit ........................................................................................................................... 11
Priority Interrupt Controller.................................................................................................. 11
Instruction Set Summary .................................................................................................... 12
Faults and Debugging.........................................................................................................12
Low Power Operation ......................................................................................................... 12
Test Features...................................................................................................................... 12
Memory-Mapped Control Registers .................................................................................... 13
Data Types and Memory Addressing Modes...................................................................... 13
Available Processors and Packages .................................................................................. 15
Pin Descriptions .................................................................................................................. 16
3.2.1 Functional Pin Definitions ...................................................................................... 16
3.2.2 80960Jx 132-Lead PGA Pinout ............................................................................. 23
3.2.3 80960Jx 132-Lead PQFP Pinout ........................................................................... 27
3.2.4 80960Jx 196-Ball MPBGA Pinout .......................................................................... 30
Absolute Maximum Ratings ................................................................................................ 35
Operating Conditions .......................................................................................................... 35
Connection Recommendations........................................................................................... 36
VCC5 Pin Requirements (VDIFF) ....................................................................................... 36
VCCPLL Pin Requirements ................................................................................................ 37
D.C. Specifications ............................................................................................................. 38
A.C. Specifications.............................................................................................................. 42
4.7.1 A.C. Test Conditions and Derating Curves ............................................................ 45
4.7.1.1 Output Delay or Hold vs. Load Capacitance .......................................... 46
4.7.1.2 T
LX
vs. AD Bus Load Capacitance......................................................... 47
4.7.1.3 ICC Active vs. Frequency ...................................................................... 49
4.7.2 A.C. Timing Waveforms ......................................................................................... 53
80960JS/JC/JT Device Identification Register.................................................................... 60
80960JD Device Identification Register .............................................................................. 61
80960JA/JF Device Identification Register ......................................................................... 62
Thermal Management Accessories .................................................................................... 68
6.1.1 Heatsinks ............................................................................................................... 68
Basic Bus States................................................................................................................. 79
Boundary-Scan Register..................................................................................................... 80
Pac kaging Information
................................................................................................................ 15
4.0
Electrical Specifications
............................................................................................................. 35
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5.0
Device Identification....................................................................................................................
59
5.1
5.2
5.3
6.0
Thermal Specifications
............................................................................................................... 63
6.1
7.0
Bus Functional Waveforms
........................................................................................................ 69
7.1
7.2
Datasheet
3
Contents
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
80960Jx Microprocessor Package Options .................................................................................. 7
80960Jx Block Diagram.............................................................................................................. 10
132-Lead Pin Grid Array Top View-Pins Facing Down............................................................... 23
132-Lead Pin Grid Array Bottom View-Pins Facing Up .............................................................. 24
132-Lead PQFP - Top View ....................................................................................................... 27
196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down ............................................ 30
196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up ........................................... 31
VCC5 Current-Limiting Resistor ................................................................................................. 36
VCCPLL Lowpass Filter ............................................................................................................. 37
A.C. Test Load............................................................................................................................ 45
Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (3.3 V Signals) .......................... 46
Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (5 V Signals) ............................. 46
Output Delay or Hold vs. Load Capacitance–80960JA/JF/JD .................................................... 47
T
LX
vs. AD Bus Load Capacitance–80960JS/JC/JT (3.3 V Signals) ......................................... 47
T
LX
vs. AD Bus Load Capacitance–80960JS/JC/JT (5 V Signals) ............................................ 48
T
LX
vs. AD Bus Load Capacitance–80960JA/JF/JD................................................................... 48
I
CC
Active (Power Supply) vs. Frequency–80960JA/JF ............................................................. 49
80960JA/JF I
CC
Active (Thermal) vs. Frequency ....................................................................... 49
80960JD I
CC
Active (Power Supply) vs. Frequency ................................................................... 50
80960JD I
CC
Active (Thermal) vs. Frequency ............................................................................ 50
80960JC I
CC
Active (Power Supply) vs. Frequency ................................................................... 51
80960JC I
CC
Active (Thermal) vs. Frequency ............................................................................ 51
80960JS I
CC
Active (Power Supply) vs. Frequency ................................................................... 52
80960JS I
CC
Active (Thermal) vs. Frequency ............................................................................ 52
CLKIN Waveform........................................................................................................................ 53
T
OV1
Output Delay Waveform .................................................................................................... 53
T
OF
Output Float Waveform ....................................................................................................... 54
T
IS1
and T
IH1
Input Setup and Hold Waveform .......................................................................... 54
T
IS2
and T
IH2
Input Setup and Hold Waveform .......................................................................... 54
T
IS3
and T
IH3
Input Setup and Hold Waveform .......................................................................... 55
T
IS4
and T
IH4
Input Setup and Hold Waveform .......................................................................... 55
T
LX
, T
LXL
and T
LXA
Relative Timings Waveform ........................................................................ 56
DT/R# and DEN# Timings Waveform......................................................................................... 56
TCK Waveform ........................................................................................................................... 57
T
BSIS1
and T
BSIH1
Input Setup and Hold Waveforms ................................................................. 57
T
BSOV1
and T
BSOF1
Output Delay and Output Float Waveform ................................................. 57
T
BSOV2
and T
BSOF2
Output Delay and Output Float Waveform ................................................. 58
T
BSIS2
and T
BSIH2
Input Setup and Hold Waveform................................................................... 58
80960JS/JC/JT Device Identification Register Fields ................................................................. 60
80960JD Device Identification Register Fields ........................................................................... 61
80960JA/JF Device Identification Register Fields ...................................................................... 62
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus................................. 69
Burst Read and Write Transactions Without Wait States, 32-Bit Bus ........................................ 70
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus .................................................. 71
Burst Read and Write Transactions Without Wait States, 8-Bit Bus .......................................... 72
Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus ..................................................................................... 73
47 Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit Bus, Little Endian ........................................................................ 74
4
Datasheet
Contents
48
49
50
51
52
53
54
HOLD/HOLDA Waveform For Bus Arbitration ............................................................................ 75
Cold Reset Waveform................................................................................................................. 76
Warm Reset Waveform .............................................................................................................. 77
Entering the ONCE State............................................................................................................ 78
Bus States with Arbitration.......................................................................................................... 80
Summary of Aligned and Unaligned Accesses (32-Bit Bus) ....................................................... 84
Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ................................... 85
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
80960Jx 3.3-V Microprocessor Family ......................................................................................... 7
80960Jx Instruction Set .............................................................................................................. 14
80960Jx Processors Available in 132-Pin PGA Package ........................................................... 15
80960Jx Processors Available in 132-Pin PQFP Package......................................................... 15
80960Jx Processors Available in Extended Temperature ......................................................... 16
80960Jx Processors Available in 196-Ball MPBGA Package..................................................... 16
Pin Description Nomenclature .................................................................................................... 17
Pin Description—External Bus Signals....................................................................................... 18
Pin Description—Processor Control Signals, Test Signals, and Power ..................................... 21
Pin Description—Interrupt Unit Signals ...................................................................................... 22
132-Lead PGA Pinout—In Signal Order ..................................................................................... 25
132-Lead PGA Pinout—In Pin Order.......................................................................................... 26
132-Lead PQFP Pinout—In Signal Order................................................................................... 28
132-Lead PQFP Pinout—In Pin Order........................................................................................ 29
196-Ball MPBGA Pinout—In Signal Order.................................................................................. 32
196-Ball MPBGA Pinout—In Pin Order ...................................................................................... 33
Absolute Maximum Ratings ........................................................................................................ 35
80960Jx Operating Conditions ................................................................................................... 35
VDIFF Parameters...................................................................................................................... 37
80960Jx D.C. Characteristics ..................................................................................................... 38
80960Jx I
CC
Characteristics ....................................................................................................... 39
80960Jx A.C. Characteristics ..................................................................................................... 42
Note Definitions for Table 22, 80960Jx AC Characteristics ........................................................ 45
80960Jx Device Type and Stepping Reference ......................................................................... 59
80960JS/JC/JT Device ID Register Field Definitions.................................................................. 60
80960JS/JC/JT Device ID Model Types ..................................................................................... 60
80960JD Device ID Field Definitions .......................................................................................... 61
80960JD Device ID Model Types ............................................................................................... 61
80960JA/JF Device ID Field Definitions ..................................................................................... 62
80960JA/JF Device ID Model Types .......................................................................................... 62
Thermal Resistance for q
CA
and q
JC
Reference Table .............................................................. 63
Maximum Ambient Temperature Reference Table ..................................................................... 63
132-Lead PGA Package Thermal Characteristics ...................................................................... 64
80960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics ......................................... 64
80960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics ......................................... 65
132-Lead PQFP Package Thermal Characteristics .................................................................... 65
Maximum T
A
at Various Airflows in °C (80960JT) ...................................................................... 66
Maximum T
A
at Various Airflows in °C (80960JC) ...................................................................... 66
Maximum T
A
at Various Airflows in °C (80960JD) ...................................................................... 67
Maximum T
A
at Various Airflows in °C (80960JS) ...................................................................... 67
Maximum T
A
at Various Airflows in °C (80960JA/JF) ................................................................. 68
Datasheet
5
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