MOSEL VITELIC
V53C16258L
HIGH PERFORMANCE
3.3 VOLT 256K X 16 EDO PAGE
MODE CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (t
RAC
)
Max. Column Address Access Time, (t
CAA
)
Min. Fast Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
40
40 ns
20 ns
15 ns
75 ns
45
45 ns
22 ns
17 ns
80 ns
50
50 ns
24 ns
19 ns
90 ns
60
60 ns
30 ns
27 ns
110 ns
Features
s
256K x 16-bit organization
s
EDO Page Mode for a sustained data rate
of 66 MHz
s
RAS access time: 40, 45, 50, 60 ns
s
Dual CAS Inputs
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s
Refresh Interval: 512 cycles/8 ms
s
Available in 40-pin 400 mil SOJ and
40/44L-pin 400 mil TSOP-II packages
s
Single +3.3V
±
0.3V Power Supply
s
TTL Interface
Description
The V53C16258L is a 262,144 x 16 bit high-
performance CMOS dynamic random access
memory. The V53C16258L offers Page mode with
Extended Data Output. An address, CAS and RAS
input capacitances are reduced to one quarter
when the x4 DRAM is used to construct the same
memory density. The V53C16258L has symmetric
address and accepts 512 cycle 8ms interval.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 512 x 16 bits,
within a page, with cycle times as short as 15ns.
The V53C16258L is ideally suited for a wide
variety of high performance portable computer
systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0
°
C to 70
°
C
Package Outline
K
•
T
•
40
•
Access Time (ns)
45
•
50
•
60
•
Power
Std.
•
Temperature
Mark
Blank
V53C16258L Rev. 1.5 May 1997
1
MOSEL VITELIC
V
5
3
C
16
2
5
8
L
V53C16258L
FAMILY
DEVICE
K (SOJ)
T (TSOP-II)
40
45
50
60
PKG
SPEED
( t
RAC
)
TEMP.
PWR.
BLANK (0°C to 70°C)
BLANK (NORMAL)
Description
SOJ
TSOP-II
Pkg.
K
T
Pin Count
40
40/44L
(40 ns)
(45 ns)
(50 ns)
(50 ns)
16258L-01
40-Pin Plastic SOJ
PIN CONFIGURATION
Top View
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
16258L-02
40/44 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
16258L-03
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
Pin Names
A
0
–A
8
RAS
UCAS
LCAS
WE
OE
I/O
1
–I/O
16
V
CC
V
SS
NC
Address Inputs
Row Address Strobe
Column Address Strobe/Upper Byte Control
Column Address Strobe/Lower Byte Control
Write Enable
Output Enable
Data Input, Output
+3.3V Supply
0V Supply
No Connect
V53C16258L Rev. 1.5 May 1997
2
MOSEL VITELIC
Absolute Maximum Ratings*
Ambient Temperature
Under Bias ..................................... –10
°
C to +80
°
C
Storage Temperature (plastic) ..... –55
°
C to +125
°
C
Voltage Relative to V
SS
.................–1.0 V to +4.6 V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
V53C16258L
Capacitance*
Symbol
C
IN1
C
IN2
C
OUT
T
A
= 25
°
C, V
CC
= 3.3 V
±
0.3V, V
SS
= 0 V
Parameter
Address Input
RAS, CAS, WE, OE
Data Input/Output
Typ.
3
4
5
Max.
4
5
7
Unit
pF
pF
pF
* Note: Capacitance is sampled and not 100% tested
Block Diagram
256K x 16
OE
WE
UCAS
LCAS
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
DATA I/O BUS
COLUMN DECODERS
Y -Y8
0
I/O 1
I/O 2
I/O 3
SENSE AMPLIFIERS
512 x 16
I/O
BUFFER
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
REFRESH
COUNTER
9
A0
A1
ADDRESS BUFFERS
AND PREDECODERS
X0 -X8
ROW
DECODERS
512
I/O 12
•
•
•
A7
A8
MEMORY
ARRAY
256K x 16
I/O 13
I/O 14
I/O 15
I/O 16
16258L-04
V53C16258L Rev. 1.5 May 1997
3
MOSEL VITELIC
DC and Operating Characteristics
(1-2)
T
A
= 0
°
C to 70
°
C, V
CC
= +3.3 V
±
0.3V, V
SS
= 0 V, unless otherwise specified.
Access
Time
V53C16258L
Min.
–10
V53C16258L
Symbol
I
LI
I
LO
I
CC1
Parameter
Input Leakage Current
(any input pin)
Output Leakage Current
(for High-Z State)
V
CC
Supply Current,
Operating
Typ.
Max.
10
Unit
µ
A
µ
A
mA
Test Conditions
V
SS
≤
V
IN
≤
V
CC
V
SS
≤
V
OUT
≤
V
CC
RAS, CAS at V
IH
t
RC
= t
RC
(min.)
Notes
–10
10
40
45
50
60
110
100
90
80
500
1, 2
I
CC2
I
CC3
V
CC
Supply Current,
TTL Standby
V
CC
Supply Current,
RAS-Only Refresh
40
45
50
60
µ
A
mA
RAS, CAS at V
IH
other inputs
≥
V
SS
t
RC
= t
RC
(min.)
2
110
100
90
80
100
90
80
70
1
I
CC4
V
CC
Supply Current,
EDO Page Mode Operation
40
45
50
60
mA
Minimum Cycle
1, 2
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
other inputs
≥
V
SS
V
CC
Supply Current,
CMOS Standby
mA
RAS=V
IH
, CAS=V
IL
1
I
CC6
100
µ
A
RAS
≥
V
CC
– 0.2 V,
CAS
≥
V
CC
– 0.2 V,
All other inputs
≥
V
SS
V
CC
V
IL
V
IH
V
OL
V
OH
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
3.0
–1
2.4
3.6
0.8
V
CC
+1
0.4
V
V
V
V
V
I
OL
= 2 mA
I
OH
= –2 mA
3
3
2.4
V53C16258L Rev. 1.5 May 1997
4
MOSEL VITELIC
T
A
= 0
°C
to 70°C, V
CC
= +3.3 V
±0.3V,
V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
40
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V53C16258L
AC Characteristics
45
50
60
Symbol
t
RAS
t
RC
t
RP
t
CSH
t
CAS
t
RCD
t
RCS
t
ASR
t
RAH
t
ASC
t
CAH
t
RSH (R)
t
CRP
t
RCH
t
RRH
t
ROH
t
OAC
t
CAC
t
RAC
t
CAA
t
LZ
t
HZ
t
AR
t
RAD
t
RSH (W)
t
CWL
t
WCS
t
WCH
t
WP
t
WCR
t
RWL
t
DS
Parameter
RAS Pulse Width
Read or Write Cycle Time
RAS Precharge Time
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay
Read Command Setup Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS Hold Time (Read Cycle)
CAS to RAS Precharge Time
Read Command Hold Time
Referenced to CAS
Read Command Hold Time
Referenced to RAS
RAS Hold Time Referenced to OE
Access Time from OE
Access Time from CAS
Access Time from RAS
Access Time from Column Address
OE or CAS to Low-Z Output
OE or CAS to High-Z Output
Column Address Hold Time from RAS
RAS to Column Address Delay Time
RAS or CAS Hold Time in Write Cycle
Write Command to CAS Lead Time
Write Command Setup Time
Write Command Hold Time
Write Pulse Width
Write Command Hold Time from RAS
Write Command to RAS Lead Time
Data in Setup Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
40
75
25
40
7
17
0
0
7
0
5
10
5
0
28
75
45
80
25
45
8
18
0
0
8
0
6
10
5
0
32
75K
50
90
30
50
9
19
0
0
9
0
7
10
5
0
36
75K
60
110
40
60
11
20
0
0
10
0
10
10
5
0
45
75K
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
4
15
0
0
0
0
ns
5
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
8
12
12
40
20
0
0
30
12
10
12
0
5
5
30
12
0
20
6
9
13
13
45
22
0
0
35
13
10
13
0
6
6
35
13
0
23
7
10
14
14
50
24
0
0
40
14
10
14
0
7
7
40
14
0
26
8
10
15
15
60
30
0
0
50
15
10
15
0
10
10
50
15
0
30
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
12, 13
11
12
6, 7, 14
6, 8, 9
6, 7, 10
16
16
V53C16258L Rev. 1.5 May 1997
5
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