If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
CMOS/TTL Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit
Duration
Junction Temperature
Storage Temperature
Lead Temperature
(Soldering, 4 sec)
MTD48 (TSSOP) Package:
DS90C363A/DS90CF363A
−0.3V to +4V
−0.3V to (V
CC
+ 0.3V)
−0.3V to (V
CC
+ 0.3V)
Continuous
+150˚C
−65˚C to +150˚C
+260˚C
Package Derating:
DS90C363A/DS90CF363A
ESD Rating
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0Ω, 200 pF)
16 mW/˚C above +25˚C
>
7 kV
>
500V
Recommended Operating
Conditions
Min Nom Max
Supply Voltage (V
CC
)
Operating Free Air
Temperature (T
A
)
Receiver Input Range
Supply Noise Voltage (V
CC
)
TxCLKIN frequency
−10 +25 +70
0
18
2.4
100
68
˚C
V
mV
PP
MHz
3.0
3.3
3.6
Units
V
Maximum Package Power Dissipation Capacity
@
25˚C
1.98 W
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
V
IH
V
IL
V
CL
I
IN
Parameter
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
I
CL
= −18 mA
V
V
LVDS DC SPECIFICATIONS
V
OD
∆V
OD
V
OS
∆V
OS
I
OS
I
OZ
Differential Output Voltage
Change in V
OD
between
complimentary output states
Offset Voltage (Note 4)
Change in V
OS
between
complimentary output states
Output Short Circuit Current
Output
TRI-STATE
®
Current
V
OUT
= 0V, R
L
= 100Ω
Power Down = 0V,
V
OUT
= 0V or V
CC
R
L
= 100Ω,
C
L
= 5 pF,
Worst Case Pattern
(Figures 1, 4 )
R
L
= 100Ω,
C
L
= 5 pF,
16 Grayscale Pattern
(Figures 2, 4 )
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
−3.5
1.125
1.25
R
L
= 100Ω
250
345
450
35
1.375
35
−5
mV
mV
V
mV
mA
µA
IN
IN
Conditions
Min
2.0
GND
Typ
Max
V
CC
0.8
Units
V
V
V
µA
µA
CMOS/TTL DC SPECIFICATIONS
−0.79
+1.8
−10
0
−1.5
+10
= 0.4V, 2.5V or V
CC
= GND
±
1
±
10
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current
Worst Case
31
33
39
23
28
33
10
43
45
52
35
40
45
55
mA
mA
mA
mA
mA
mA
µA
ICCTG
Transmitter Supply Current
16 Grayscale
ICCTZ
Transmitter Supply Current
Power Down
Power Down = Low
Driver Outputs in TRI-STATE
®
under
Power Down Mode
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2:
Typical values are given for V
CC
= 3.3V and T
A
= +25C.
Note 3:
Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
OD
and
∆V
OD
).
Note 4:
V
OS
previously referred as V
CM
.
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2
DS90C363A/DS90CF363A
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCIT
TCIP
TCIH
TCIL
TxCLK IN Period
(Figure 6 )
TxCLK IN High Time
(Figure 6 )
TxCLK IN Low Time
(Figure 6 )
Parameter
TxCLK IN Transition Time
(Figure 5 )
14.7
0.35T
0.35T
T
0.5T
0.5T
Min
Typ
Max
5
55.6
0.65T
0.65T
Units
ns
ns
ns
ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
LHLT
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TSTC
THTC
TCCD
TJCC
Parameter
LVDS Low-to-High Transition Time
(Figure 4 )
LVDS High-to-Low Transition Time
(Figure 4 )
Transmitter Output Pulse Position for Bit 0
(Figure 11 )
(Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0
(Figure 11 )
(Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0
(Figure 11 )
(Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxIN Setup to TxCLK IN
(Figure 6 )
TxIN Hold to TxCLK IN
(Figure 6 )
TxCLK IN to TxCLK OUT Delay
(Figure 7 )
T
A
=25˚C, V
CC
=3.3V
TxCLK IN to TxCLK OUT Delay
(Figure 7 )
Transmitter Jitter Cycle-to-Cycle
(Figures 12, 13 )
(Note 6)
f = 65 MHz
f = 40 MHz
f = 32.5 MHz
TPLLS
TPDD
Transmitter Phase Lock Loop Set
(Figure 8 )
Transmitter Power Down Delay
(Figure 10 )
f = 32.5 MHz
f = 40 MHz
f = 65 MHz
−0.30
1.90
4.10
6.30
8.50
10.70
12.90
−0.35
3.22
6.79
10.36
13.93
17.51
21.08
−0.40
4.00
8.40
12.80
17.20
21.60
26.00
2.5
0
3
3
175
240
260
5.5
7.0
225
380
400
10
100
Min
Typ
0.75
0.75
0
2.20
4.40
6.60
8.80
11.00
13.20
0
3.57
7.14
10.71
14.28
17.86
21.43
0
4.40
8.80
13.20
17.60
22.00
26.40
Max
1.5
1.5
0.20
2.40
4.60
6.80
9.00
11.20
13.40
0.35
3.92
7.49
11.06
14.63
18.21
21.78
0.40
4.80
9.20
13.60
18.00
22.40
26.80
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ms
ns
Note 5:
The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6:
The Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. Output jitter is measured with a
cycle-to-cycle jitter of 3ns applied to the input clock signal. A jitter event of 3ns, represents worse case jump in the clock edge from most Graphics controller VGA
chips currently available. This parameter is used when calculating system margin (RSKM). See Figures 12, 13 and AN-1059.
3
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DS90C363A/DS90CF363A
AC Timing Diagrams
10013804
FIGURE 1. “Worst Case” Test Pattern
10013805
FIGURE 2. “16 Grayscale” Test Pattern
(Notes 7, 8, 9, 10)
Note 7:
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8:
The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9:
Figures 1, 2
show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 10:
Recommended pin to signal mapping. Customer may choose to define differently.
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