EEWORLDEEWORLDEEWORLD

Part Number

Search

PC8548EVZFAVJA

Description
Microprocessor, 32-Bit, 1500MHz, CMOS, PBGA783, 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size2MB,115 Pages
Manufacturere2v technologies
Download Datasheet Parametric View All

PC8548EVZFAVJA Overview

Microprocessor, 32-Bit, 1500MHz, CMOS, PBGA783, 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783

PC8548EVZFAVJA Parametric

Parameter NameAttribute value
Makere2v technologies
Parts packaging codeBGA
package instructionBGA,
Contacts783
Reach Compliance Codeunknown
ECCN code3A001.A.3
Address bus width64
bit size32
boundary scanYES
maximum clock frequency66 MHz
External data bus width64
FormatFLOATING POINT
Integrated cacheYES
JESD-30 codeS-PBGA-B783
JESD-609 codee0
length29 mm
low power modeYES
Number of terminals783
Maximum operating temperature110 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Maximum seat height3.38 mm
speed1500 MHz
Maximum supply voltage1.155 V
Minimum supply voltage1.045 V
Nominal supply voltage1.1 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD SILVER
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width29 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR
PC8548E
PowerQUICC III Integrated Processor
Datasheet
Features
Embedded e500 Core, Initial Offerings up to 1.2 GHz
– Dual Dispatch Superscalar, 7-stage Pipeline Design with out-of-order Issue and
Execution
– 3065 MIPS at 1333 MHz (Estimated Dhrystone 2.1)
36-bit Physical Addressing
Enhanced Hardware and Software Debug Support
Double-precision Embedded Scalar and Vector Floating-point APUs
Memory Management Unit (MMU)
Integrated L1/L2 Cache
– L1 Cache-32 KB Data and 32 KB Instruction Cache with Line-locking Support
– L2 Cache-512 KB (8-Way Set Associative); 512 KB/256 KB/128 KB/64 KB Can Be Used As SRAM
– L1 and L2 Hardware Coherency
– L2 Configurable As SRAM, Cache and I/O Transactions Can Be Stashed Into L2 Cache Regions
Integrated DDR Memory Controller With Full ECC Support, Supporting:
– 200 MHz Clock Rate (400 MHz Data Rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM
Integrated Security Engine Supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 Encryption
Algorithms
Four On-chip Triple-speed Ethernet Controllers (GMACs) Supporting 10- and 100-Mbps, and 1-Gbps Ethernet/IEEE*802.3
Networks with MII, RMII, GMII, RGMII, RTBI and TBI Physical Interfaces
– TCP/IP Checksum Acceleration
– Advanced QoS Features
General-purpose I/O (GPIO)
Serial RapidIO and PCI Express High-speed Interconnect Interfaces, Supporting
– Single x8 PCI Express, or Single x4 PCI Express and Single 4x Serial RapidIO
On-chip Network (OCeaN) Switch Fabric
Multiple PCI Interface Support
– 64-bit PCI 2.2 Bus Controller (Up to 66 MHz, 3.3V I/O)
– 64-bit PCI-X Bus Controller (Up to 133 MHz, 3.3V I/O), or Flexibility to Configure Two 32-bit PCI Controllers
166 MHz, 32-bit, 3.3V I/O, Local Bus with Memory Controller
Integrated Four-channel DMA Controller
Dual I2C and Dual Universal Asynchronous Receiver/Transmitter (DUAR) Support
Programmable Interrupt Controller (PIC), IEEE 1149.1 JTAG Test Access Port
1.1V Core Voltage with 3.3V and 2.5V I/O, 783-pin HITCE Package
Visit our website: www.e2v.com
for the latest version of the datasheet
e2v semiconductors SAS 2010
0831H–HIREL–11/10
【Course Recommendation】+ C2000 Basics
The course I recommend is "C2000 Basics", the course link address is: [url]https://training.eeworld.com.cn/course/3580/learn?iscs=1#lesson/7070[/url] This lecture covers the development history of C20...
cquwuqiang Microcontroller MCU
powerpc handouts
I found a PowerPC handout on the Internet. Since there is very little information of this kind, I have collected it here....
bluehacker NXP MCU
Fast Input/Output Registers约束
In order to ensure the timing performance during design, some constraints are often added so that the layout and routing can be optimized or go according to our wishes. In the past, we were quite unfa...
eeleader FPGA/CPLD
Who knows this error found illegal attempt to declare homograph of label
--DDPB.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY DDPB ISPORT(START,WCLK:IN STD_LOGIC;CLK1HZ:IN STD_LOGIC;DDBZ:OUT STD_LOGIC);...
ATT001 Embedded System
Errors that occur when multiple source files use global variables
main.c file #include "menu.h" volatile unsigned char key=0; void INT1_Key() interrupt 2 { get(key); } main() { menu(); } main.h file #ifndef _main_h_ #define _main_h_ extern volatile unsigned char key...
corsair0101 Embedded System
STM32+SDIO+FATFS Example
...
banana stm32/stm8

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1524  1455  346  1903  1738  31  30  7  39  35 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号