Freescale Semiconductor
Technical Data
MPC8540EC
Rev. 3.1, 12/2004
MPC8560
Integrated Processor
Hardware Specifications
The MPC8560 contains a PowerPC™ processor core. The
MPC8560 integrates a processor that implements the PowerPC
architecture with system logic required for networking, storage,
and general-purpose embedded applications. For functional
characteristics of the processor, refer to the
MPC8560
PowerQUICC III™ Integrated Communications Processor
Preliminary Reference Manual.
To locate any published errata or updates for this document,
contact your Freescale sales office.
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 19
DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Ethernet: Three-Speed, MII Management . . . . . . . . 25
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 72
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
System Design Information . . . . . . . . . . . . . . . . . . . 96
Document Revision History . . . . . . . . . . . . . . . . . . 102
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 105
1
Overview
The following section provides a high-level overview of the
MPC8560 features.
Figure 1
shows the major functional units
within the MPC8560.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Overview
DDR
SDRAM
DDR SDRAM Controller
I
2
C Controller
256KB
L2-Cache/
SRAM
e500
Coherency
Module
e500 Core
32 KB L1
I Cache
32 KB L1
D Cache
GPIO
32b
IRQs
Local Bus Controller
Programmable
Interrupt Controller
Serial
DMA
ROM
I-Memory
Core Complex Bus
CPM
RapidIO Controller
OCeaN
PCI Controller
DMA Controller
MPHY
UTOPIAs
TC - Layer
Time Slot Assigner
Time Slot Assigner
RapidIO-8
16 Gb/s
PCI 64b
133 MHz
MCC
MCC
FCC
FCC
FCC
SCC
SCC
SCC
SCC
SPI
I2C
Serial Interfaces
MIIs,
RMIIs
TDMs
I/Os
DPRAM
RISC
Engine
Parallel I/O
Baud Rate
Generators
Timers
CPM
Interrupt
Controller
10/100/1000 MAC
10/100/1000 MAC
MII, GMII, TBI,
RTBI, RGMIIs
Figure 1. MPC8560 Block Diagram
1.1 Key Features
The following lists an overview of the MPC8560 feature set.
•
High-performance, 32-bit Book E–enhanced core that implements the PowerPC architecture
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked
entirely or on a per-line basis. Separate locking for instructions and data
— Memory management unit (MMU) especially designed for embedded applications
— Enhanced hardware and software debug support
— Performance monitor facility (similar to but different from the MPC8560 performance monitor
described in Chapter 18, “Performance Monitor.”
High-performance RISC CPM operating at up to 333 MHz
— CPM software compatibility with previous PowerQUICC families
— One instruction per clock
— Executes code from internal ROM or instruction RAM
— 32-bit RISC architecture
— Tuned for communication environments: instruction set supports CRC computation and bit
manipulation.
— Internal timer
•
MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
2
Freescale Semiconductor
Overview
•
— Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and virtual DMA
channels for each peripheral controller
— Handles serial protocols and virtual DMA.
— Three full-duplex fast serial communications controllers (FCCs) that support the following protocols:
– ATM protocol through UTOPIA interface (FCC1 and FCC2 only)
– IEEE802.3/Fast Ethernet
– HDLC
– Totally transparent operation
— Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent channels
at 64 Kbps each, multiplexed on up to 8 TDM interfaces
— Four full-duplex serial communications controllers (SCCs) that support the following protocols:
– High level/synchronous data link control (HDLC/SDLC)
– LocalTalk (HDLC-based local area network protocol)
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART (1x clock mode)
– Binary synchronous communication (BISYNC)
– Totally transparent operation
— Serial peripheral interface (SPI) support for master or slave
— I
2
C bus controller
— Time-slot assigner supports multiplexing of data from any of the SCCs and FCCs onto eight
time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following TDM
formats:
– T1/CEPT lines
– T3/E3
– Pulse code modulation (PCM) highway interface
– ISDN primary rate
– Freescale interchip digital link (IDL)
– General circuit interface (GCI)
— User-defined interfaces
— Eight independent baud rate generators (BRGs)
— Four general-purpose 16-bit timers or two 32-bit timers
— General-purpose parallel ports—16 parallel I/O lines with interrupt capability
— Supports inverse muxing of ATM cells (IMA)
256 Kbyte L2 cache/SRAM
— Can be configured as follows
– Full cache mode (256-Kbyte cache).
– Full memory-mapped SRAM mode (256-Kbyte SRAM mapped as a single 256-Kbyte block or two
128-Kbyte blocks)
– Half SRAM and half cache mode (128-Kbyte cache and 128-Kbyte memory-mapped SRAM)
— Full ECC support on 64-bit boundary in both cache and SRAM modes
MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
Freescale Semiconductor
3
Overview
•
•
•
— Cache mode supports instruction caching, data caching, or both
— External masters can force data to be allocated into the cache through programmed memory ranges or
special transaction types (stashing)
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines. Individual line locks are set and cleared through
Book E instructions or by externally mastered transactions
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses
— SRAM features include the following:
– I/O devices access SRAM regions by marking transactions as snoopable (global)
– Regions can reside at any aligned location in the memory map
– Byte accessible ECC is protected using read-modify-write transactions accesses for smaller than
cache-line accesses.
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 32-bit address space
— Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI/PCI-X
– Four inbound windows plus a default and configuration window on RapidIO
– Four outbound windows plus default translation for PCI
– Eight outbound windows plus default translation for RapidIO
DDR memory controller
— Programmable timing supporting DDR-1 SDRAM
— 64-bit data interface, up to 333-MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL2 compatible I/O
RapidIO interface unit
— 8-bit RapidIO I/O and messaging protocols
— Source-synchronous double data rate (DDR) interfaces
— Supports small type systems (small domain, 8-bit device ID)
MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
4
Freescale Semiconductor
Overview
•
•
•
•
•
— Supports four priority levels (ordering within a level)
— Reordering across priority levels
— Maximum data payload of 256 bytes per packet
— Packet pacing support at the physical layer
— CRC protection for packets
— Supports atomic operations increment, decrement, set, and clear
— LVDS signaling
RapidIO–compliant message unit
— One inbound data message structure (inbox)
— One outbound data message structure (outbox)
— Supports chaining and direct modes in the outbox
— Support of up to 16 packets per message
— Support of up to 256 bytes per packet and up to 4 Kbytes of data per message
— Supports one inbound doorbell message structure
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
— Supports connection of an external interrupt controller such as the 8259 programmable interrupt
controller
— Four global high resolution timers/counters that can generate interrupts
— Supports 22 other internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
— Interrupt summary registers allow fast identification of interrupt source
I
2
C controller
— Two-wire interface
— Multiple master support
— Master or slave I
2
C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset via the I
2
C interface
— Can be used to initialize configuration registers and/or memory
— Supports extended I
2
C addressing mode
— Data integrity checked with preamble signature and CRC
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 166 MHz
— Eight chip selects support eight external slaves
MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
Freescale Semiconductor
5
京公网安备 11010802033920号
EEWORLD
