If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 14)
Supply Voltage (V
+
− V
−
)
Voltage at Any Pin
Input Current at Any Pin (Note 2)
Package Input Current (Note 2)
Power Dissipation (Note 3)
Storage Temperature
ESD Susceptability (Note 11)
Soldering Information
N Package: 10 sec.
16V
V
+
+ 0.3V
V
−
− 0.3V
5 mA
20 mA
500 mW
150˚C
2000V
260˚C
J Package: 10 sec.
300˚C
SO Package:
Vapor Phase (60 sec.)
215˚C
Infrared (15 sec.)
220˚C
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” (Appendix D) for other methods of
soldering surface mount devices.
Operating Ratings
(Note 1)
Temperature Range
LMF100CCN
LMF100CIWM
Supply Voltage
T
MIN
≤
T
A
≤
T
MAX
0˚C
≤
T
A
≤
+70˚C
−40˚C
≤
T
A
≤
+85˚C
4V
≤
V
+
− V
−
≤
15V
Electrical Characteristics
The following specifications apply for Mode 1, Q = 10 (R
1
= R
3
= 100k, R
2
= 10k), V
+
= +5V and V
−
= −5V unless otherwise
specified.
Boldface limits apply for T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25˚C.
LMF100CCN
Symbol
Parameter
Conditions
Typical
(Note 8)
9
0.1
100
5.0
3.5
V
Pin12
= 5V or 0V
f
CLK
= 1 MHz
Q = 10, Mode 1
V
Pin12
= 5V or 0V
f
CLK
= 1 MHz
f
CLK
= 1 MHz
R
1
= R
2
= 10k
f
CLK
= 250 kHz
V
OS1
V
OS2
V
OS3
DC Offset Voltage (Note 5)
DC Offset Voltage (Note 5)
DC Offset Voltage (Note 5)
Crosstalk (Note 6)
Output Noise (Note 12)
f
CLK
= 250 kHz
f
CLK
= 250 kHz
f
CLK
= 250 kHz
A Side to B Side or
B Side to A Side
f
CLK
= 250 kHz
20 kHz Bandwidth
100:1 Mode
Clock Feedthrough
(Note 13)
V
OUT
Minimum Output
Voltage Swing
N
BP
LP
S
A/B
= V
+
S
A/B
= V
−
Tested
Limit
(Note 9)
13
Design
Limit
(Note 10)
13
Typical
(Note 8)
9
0.1
100
5.0
3.5
LMF100CIWM
Tested
Limit
(Note 9)
13
Design
Limit
(Note 10)
Units
I
s
f
0
f
CLK
f
CLK
/f
0
Maximum Supply Current
Center Frequency
Range
Clock Frequency
Range
MIN
MAX
MIN
MAX
f
CLK
= 250 kHz
No Input Signal
mA
Hz
kHz
Hz
MHz
Clock to Center Frequency
Ratio Deviation
Q Error (MAX) (Note 4)
±
0.2
±
0.5
±
0.8
±
5
±
0.8
±
6
±
0.2
±
0.5
±
0.8
±
6
%
%
H
OBP
H
OLP
Bandpass Gain at f
0
DC Lowpass Gain
0
0
±
0.4
±
0.2
±
15
±
80
±
70
±
40
±
0.4
±
0.2
±
15
±
80
±
70
±
60
0
0
±
0.4
±
0.2
±
15
±
80
±
70
±
60
dB
dB
mV
mV
mV
mV
dB
±
5.0
±
30
±
15
±
15
−60
40
320
300
6
+4.0
−4.7
+3.9
−4.6
5
20
±
5.0
±
30
±
15
±
15
−60
40
320
300
6
µV
mV
f
CLK
= 250 kHz 100:1 Mode
R
L
= 5k
(All Outputs)
R
L
= 3.5k
(All Outputs)
±
3.8
±
3.7
+4.0
−4.7
+3.9
−4.6
5
20
12
45
±
3.7
V
V
MHz
V/µs
mA
mA
GBW
SR
I
sc
Op Amp Gain BW Product
Op Amp Slew Rate
Maximum Output
Short
Circuit Current
(Note 7)
Source
Sink
(All Outputs)
12
45
www.national.com
2
Electrical Characteristics
(Continued)
The following specifications apply for Mode 1, Q = 10 (R
1
= R
3
= 100k, R
2
= 10k), V
+
= +5V and V
−
= −5V unless otherwise
specified.
Boldface limits apply for T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25˚C.
LMF100CCN
Symbol
Parameter
Conditions
Typical
(Note 8)
Tested
Limit
(Note 9)
10
Design
Limit
(Note 10)
Typical
(Note 8)
LMF100CIWM
Tested
Limit
(Note 9)
10
Design
Limit
(Note 10)
Units
I
IN
Input Current on Pins: 4, 5,
6, 9, 10, 11, 12, 16, 17
µA
Electrical Characteristics
The following specifications apply for Mode 1, Q = 10 (R
1
= R
3
= 100k, R
2
= 10k), V
+
= +2.50V and V
−
= −2.50V unless oth-
erwise specified.
Boldface limits apply for T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25˚C.
LMF100CCN
Symbol
Parameter
Conditions
Typical
(Note 8)
Tested
Limit
(Note 9)
12
Design
Limit
(Note
10)
12
Typical
(Note 8)
LMF100CIWM
Tested
Limit
(Note 9)
12
Design
Limit
(Note
10)
Units
I
s
f
0
f
CLK
f
CLK
/f
0
Maximum Supply
Current
Center Frequency
Range
Clock Frequency
Range
Clock to Center
Frequency Ratio Deviation
Q Error (MAX)
(Note 4)
MIN
MAX
MIN
MAX
f
CLK
= 250 kHz
No Input Signal
8
0.1
50
5.0
1.5
8
0.1
50
5.0
1.5
mA
Hz
kHz
Hz
MHz
V
Pin12
= 2.5V or 0V
f
CLK
= 1 MHz
Q = 10, Mode 1
V
Pin12
= 5V or 0V
f
CLK
= 1 MHz
f
CLK
= 1 MHz
R
1
= R
2
= 10k
f
CLK
= 250 kHz
f
CLK
= 250 kHz
f
CLK
= 250 kHz
f
CLK
= 250 kHz
A Side to B Side or
B Side to A Side
f
CLK
= 250 kHz
100:1 Mode
N
LP
S
A/B
= V
+
S
A/B
= V
−
±
0.2
±
1
±
1
±
0.2
±
1
%
±
0.5
0
0
±
5
±
0.4
±
0.2
±
15
±
60
±
50
±
25
±
8
±
0.5
±
0.2
±
15
±
60
±
60
±
30
±
0.5
0
0
±
8
±
0.5
±
0.2
±
15
±
60
±
60
±
30
%
dB
dB
mV
mV
mV
mV
dB
H
OBP
H
OLP
V
OS1
V
OS2
V
OS3
Bandpass Gain at f
0
DC Lowpass Gain
DC Offset Voltage (Note 5)
DC Offset Voltage (Note 5)
DC Offset Voltage (Note 5)
Crosstalk (Note 6)
Output Noise (Note 12)
±
5.0
±
20
±
10
±
10
−65
25
250
220
2
+1.6
−2.2
+1.5
−2.1
5
18
±
5.0
±
20
±
10
±
10
−65
25
250
220
2
20 kHz Bandwidth BP
Clock Feedthrough (Note 13)
V
OUT
Minimum Output
Voltage Swing
f
CLK
= 250 kHz 100:1 Mode
R
L
= 5k
(All Outputs)
R
L
= 3.5k
(All outputs)
GBW
SR
I
sc
Op Amp Gain BW Product
Op Amp Slew Rate
Maximum Output
Short Circuit
Current (Note 7)
Source
Sink
(All Outputs)
µV
mV
±
1.5
±
1.4
+1.6
−2.2
+1.5
−2.1
5
18
10
20
±
1.4
V
V
MHz
V/µs
mA
mA
10
20
3
www.national.com
Logic Input Characteristics
Boldface limits apply for T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25˚C.
LMF100CCN
Parameter
Conditions
Typical
(Note 8)
Tested
Limit
(Note 9)
CMOS Clock
Input Voltage
MIN Logical “1”
MAX Logical “0”
MIN Logical “1”
MAX Logical “0”
TTL Clock
Input Voltage
MIN Logical “1”
MAX Logical “0”
MIN Logical “1”
MAX Logical “0”
CMOS Clock
Input Voltage
MIN Logical “1”
MAX Logical “0”
MIN Logical “1”
MAX Logical “0”
TTL Clock
Input Voltage
MIN Logical “1”
MAX Logical “0”
V
+
= +5V, V
−
= −5V,
V
LSh
= 0V
V
+
= +10V, V
−
= 0V,
V
LSh
= +5V
V
+
= +5V, V
−
= −5V,
V
LSh
V
LSh
= 0V
= 0V
V
+
= +10V, V
−
= 0V,
V
+
= +2.5V, V
−
= −2.5V,
V
LSh
= 0V
V
+
= +5V, V
−
= 0V,
V
LSh
= +2.5V
V
+
= +5V, V
−
= 0V,
V
LSh
= 0V, V
D+
= 0V
+3.0
−3.0
+8.0
+2.0
+2.0
+0.8
+2.0
+0.8
+1.5
−1.5
+4.0
+1.0
+2.0
+0.8
Design
Limit
(Note 10)
+3.0
−3.0
+8.0
+2.0
+2.0
+0.8
+2.0
+0.8
+1.5
−1.5
+4.0
+1.0
+2.0
+0.8
Typical
(Note 8)
LMF100CIWM
Tested
Limit
(Note 9)
+3.0
−3.0
+8.0
+2.0
+2.0
+0.8
+2.0
+0.8
+1.5
−1.5
+4.0
+1.0
+2.0
+0.8
Design
Limit
(Note 10)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Units
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not op-
erated under the listed test conditions.
Note 2:
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
<
V
−
or V
IN
>
V
+
) the absolute value of current at that pin should be limited
to 5 mA or less. The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mA.
Note 3:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
,
θ
JA
, and the ambient temperature, T
A
. The maximum
allowable power dissipation at any temperature is P
D
= (T
JMAX
− T
A
)/θ
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
T
JMAX
= 125˚C, and the typical junction-to-ambient thermal resistance of the LMF100CIN when board mounted is 55˚C/W. For the LMF100CIWM this number is
66˚C/W.
Note 4:
The accuracy of the Q value is a function of the center frequency (f
0
). This is illustrated in the curves under the heading “Typical Peformance Characteristics”.
Note 5:
V
os1
, V
os2
, and V
os3
refer to the internal offsets as discussed in the Applications Information section 3.4.
Note 6:
Crosstalk between the internal filter sections is measured by applying a 1 V
RMS
10 kHz signal to one bandpass filter section input and grounding the input
of the other bandpass filter section. The crosstalk is the ratio between the output of the grounded filter section and the 1 V
RMS
input signal of the other section.
Note 7:
The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output
to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 8:
Typicals are at 25˚C and represent most likely parametric norm.
Note 9:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10:
Design limits are guaranteed to National’s AOQL (Average Outgoing Quality Level) but are not 100% tested.
Note 11:
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 12:
In 50:1 mode the output noise is 3 dB higher.
Note 13:
In 50:1 mode the clock feedthrough is 6 dB higher.
Note 14:
A military RETS specification is available upon request.
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