PALCE20V8H-25PC datasheet, PDF

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PALCE20V8H-25PC: DescriptionEE PLD, 25ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, SKINNY, PLASTIC, DIP-24; CategoryProgrammable logic devices Programmable logic; File Size480KB，25 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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PALCE20V8H-25PC Overview

EE PLD, 25ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, SKINNY, PLASTIC, DIP-24

PALCE20V8H-25PC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	DIP
package instruction	DIP, DIP24,.3
Contacts	24
Reach Compliance Code	not_compliant
ECCN code	EAR99
Architecture	PAL-TYPE
maximum clock frequency	37 MHz
JESD-30 code	R-PDIP-T24
JESD-609 code	e0
length	31.75 mm
Dedicated input times	12
Number of I/O lines	8
Number of entries	20
Output times	8
Number of product terms	64
Number of terminals	24
Maximum operating temperature	75 °C
Minimum operating temperature
organize	12 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Programmable logic type	EE PLD
propagation delay	25 ns
Certification status	Not Qualified
Maximum seat height	5.334 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm

PALCE20V8H-25PC Preview

COM'L: H-5/7/10/15/25, Q-15/25

IND: H-15/25, Q-20/25

PALCE20V8 Family

EE CMOS 24-Pin Universal

Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible with all PAL

20V8 devices

Electrically erasable CMOS technology provides reconﬁgurable logic and full testability

High-speed CMOS technology

GENERAL DESCRIPTION

The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-

erasable CMOS technology. Its macrocells provide a universal device architecture. The

PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series

devices and most 24-pin combinatorial PAL devices.

Device logic is automatically conﬁgured according to the user’s design speciﬁcation. A design is

implemented using any of a number of popular design software packages, allowing automatic

creation of a programming ﬁle based on Boolean or state equations. Design software also veriﬁes

the design and can provide test vectors for the ﬁnished device. Programming can be

accomplished on standard PAL device programmers.

The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to

implement complex logic functions easily and efﬁciently. Multiple levels of combinatorial logic

can always be reduced to sum-of-products form, taking advantage of the very wide input gates

available in PAL devices. The equations are programmed into the device through ﬂoating-gate

cells in the AND logic array that can be erased electrically.

Publication#

16491

Amendment/0

Rev:

Issue Date:

September 2000

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— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

Direct plug-in replacement for a wide range of 24-pin PAL devices

Programmable enable/disable control

Outputs individually programmable as registered or combinatorial

Peripheral Component Interconnect (PCI) compliant

Preloadable output registers for testability

Automatic register reset on power-up

Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages

Extensive third-party software and programmer support

Fully tested for 100% programming and functional yields and high reliability

Programmable output polarity

5-ns version utilizes a split leadframe for improved performance

The ﬁxed OR array allows up to eight data product terms per output for logic functions. The

sum of these products feeds the output macrocell. Each macrocell can be programmed as

registered or combinatorial with an active-high or active-low output. The output conﬁguration

is determined by two global bits and one local bit controlling four multiplexers in each

macrocell.

BLOCK DIAGRAM

I1 – I10

CLK/I

Input

Mux.

MACRO

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Programmable AND Array

40 x 64

MACRO

I/O

MACRO

Input

Mux.

I/O

16491E

FUNCTIONAL DESCRIPTION

The PALCE20V8 is a universal PAL device. It has eight independently conﬁgurable macrocells

(MC

-MC

). Each macrocell can be conﬁgured as a registered output, combinatorial output,

combinatorial I/O, or dedicated input. The programming matrix implements a programmable

AND logic array, which drives a ﬁxed OR logic array. Buffers for device inputs have

complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve

either as array inputs or as clock (CLK) and output enable (OE) for all ﬂip-ﬂops.

Unused input pins should be tied directly to V

or GND. Product terms with all bits

unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true

and complement of any input signal connected assume a logical LOW state.

The programmable functions on the PALCE20V8 are automatically conﬁgured from the user’s

design speciﬁcation, which can be in a number of formats. The design speciﬁcation is processed

PALCE20V8 Family

by development software to verify the design and create a programming ﬁle. This ﬁle, once

downloaded to a programmer, conﬁgures the device according to the user’s desired function.

The user is given two design options with the PALCE20V8. First, it can be programmed as an

emulated PAL device. This includes the PAL20R8 series and most 24-pin combinatorial PAL

devices. The PAL device programmer manufacturer will supply device codes for the standard

PAL architectures to be used with the PALCE20V8. The programmer will program the PALCE20V8

to the corresponding PAL device architecture. This allows the user to use existing standard PAL

device JEDEC ﬁles without making any changes to them. Alternatively, the device can be

programmed directly as a PALCE20V8. Here the user must use the PALCE20V8 device code. This

option provides full utilization of the macrocells, allowing non-standard architectures to be built.

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SL0

SG1

SL1

CLK

*SG1

Adjacent

Macrocell

I/O

SL0

From

Adjacent

16491E

*In macrocells MC

and MC

, SG1 is replaced by SG0 on the feedback multiplexer.

Figure 1. PALCE20V8 Macrocell

PALCE20V8 Family

CONFIGURATION OPTIONS

Each macrocell can be conﬁgured as one of the following: registered output, combinatorial

output, combinatorial I/O or dedicated input. In the registered output conﬁguration, the output

buffer is enabled by the OE pin. In the combinatorial conﬁguration, the buffer is either controlled

by a product term or always enabled. In the dedicated input conﬁguration, the buffer is always

disabled. A macrocell conﬁgured as a dedicated input derives the input signal from an adjacent

I/O.

The macrocell conﬁgurations are controlled by the conﬁguration control word. It contains 2

global bits (SG0 and SG1) and 16 local bits (SL0

through SL0

and SL1

through SL1

). SG0

determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will

emulate a PAL20R8 family or a combinatorial device. Within each macrocell, SL0

, in conjunction

with SG1, selects the conﬁguration of the macrocell and SL1

sets the output as either active low

or active high.

The conﬁguration bits work by acting as control inputs for the multiplexers in the macrocell.

There are four multiplexers: a product term input, an enable select, an output select, and a

feedback select multiplexer. SG1 and SL0

are the control signals for all four multiplexers. In MC

and MC

, SG0 replaces SG1 on the feedback multiplexer.

These conﬁgurations are summarized in Table 1 and illustrated in Figure 2.

If the PALCE20V8 is conﬁgured as a combinatorial device, the CLK and OE pins may be available

as inputs to the array. If the device is conﬁgured with registers, the CLK and OE pins cannot be

used as data inputs.

Registered Output Conﬁguration

The control bit settings are SG0 = 0, SG1 = 1 and SL0

= 0. There is only one registered

conﬁguration. All eight product terms are available as inputs to the OR gate. Data polarity is

determined by SL1

. SL1

is an input to the exclusive-OR gate which is the D input to the ﬂip-

ﬂop. SL1

is programmed as 1 for inverted output or 0 for non-inverted output. The ﬂip-ﬂop is

loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The

output buffer is enabled by OE.

Combinatorial Conﬁgurations

The PALCE20V8 has three combinatorial output conﬁgurations: dedicated output in a non-

registered device, I/O in a non-registered device and I/O in a registered device.

Dedicated Output in a Non-Registered Device

The control settings are SG0 = 1, SG1 = 0, and SL0

= 0. All eight product terms are available to

the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the

exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode.

Note:

1. The pin number without parentheses refers to the SKINNY DIP package. The pin number in parentheses refers to the PLCC

package.

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PALCE20V8 Family

Dedicated Input in a Non-Registered Device

The control bit settings are SG0 = 1, SG1 = 0 and SL0

= 1. The output buffer is disabled. The

feedback signal is an adjacent I/O pin.

Combinatorial I/O in a Non-Registered Device

The control settings are SG0 = 1, SG1 = 1, and SL0

= 1. Only seven product terms are available

to the OR gate. The eighth product term is used to enable the output buffer. The signal at the

I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used

as an input.

Combinatorial I/O in a Registered Device

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Table 1. Macrocell Conﬁguration

Devices

Emulated

SG0

SG1

Cell

Conﬁguration

SL0X

Registered Output

Combinatorial

I/O

PAL20R8, 20R6,

20R4

PAL20R6, 20R4

The control bit settings are SG0=0,SG1=1 and SL0

=1. Only seven product terms are available

to the OR gate. The eighth product term is used as the output enable. The feedback signal is the

corresponding I/O signal.

Cell

Conﬁguration

Devices

Emulated

SG0

SG1

SL0X

Device Uses Registers

Device Uses No Registers

Combinatorial

Output

Input

PAL20L2, 18L4,

16L6, 14L8

PAL20L2, 18L4, 16L6

PAL20L8

Combinatorial

I/O

PALCE20V8 Family

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