STLVDS3487BD datasheet, PDF - EEWORLD Datasheet

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STLVDS3487BD: DescriptionQUAD LINE DRIVER, PDSO16, SOP-16; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size333KB，13 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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STLVDS3487BD Overview

QUAD LINE DRIVER, PDSO16, SOP-16

STLVDS3487BD Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	SOIC
package instruction	SOP, SOP16,.25
Contacts	16
Reach Compliance Code	compliant
ECCN code	EAR99
Differential output	YES
Number of drives	4
High level input current maximum value	0.00002 A
Input properties	STANDARD
Interface integrated circuit type	LINE DRIVER
Interface standards	EIA-644; TIA-644
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	9.9 mm
Humidity sensitivity level	3
Number of functions	4
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Minimum output swing	0.247 V
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum receive delay
Number of receiver bits	4
Maximum seat height	1.75 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
maximum transmission delay	2.5 ns
width	3.9 mm

STLVDS3487BD Preview

STLVDS3487

HIGH SPEED

DIFFERENTIAL LINE DRIVERS

MEETS OR EXCEEDS THE

REQUIREMENTS OF ANSI TIA/EIA-644

STANDARD

LOW VOLTAGE DIFFERENTIAL SIGNALING

WITH TYPICAL OUTPUT VOLTAGE OF

350mV AND A 100Ω LOAD

TYPICAL OUTPUT VOLTAGE RISE AND

FALL TIMES OF 750ps (400Mbps)

TYPICAL PROPAGATION DELAY TIMES OF

1.7ns

OPERATES FROM A SINGLE 3.3V SUPPLY

POWER DISSIPATION 25mW TYPICAL PER

DRIVER AT 200MHz

DRIVER AT HIGH IMPEDANCE WHEN

DISABLED OR WITH V

=0V

PIN COMPATIBLE WITH THE MC3487 AND

SN65LVD3487

LOW VOLTAGE TTL (LVTTL) LOGIC INPUT

LEVELS

SOP

TSSOP

DESCRIPTION

The STLVDS3487 is a quad differential line

drivers

that

implements

the

electrical

characteristics of low voltage differential signaling

(LVDS). This signaling technique lowers the

output voltage levels of 5V differential standard

levels (such as TIA/EIA-422B) to reduce the

power, increase the switching speeds and allows

ORDERING CODES

Type

STLVDS3487BD

STLVDS3487BDR

STLVDS3487BTR

Temperature

Range

-40 to 85 °C

operations with a 3.3V supply rail. Any of the four

current mode drivers will deliver a minimum

differential output voltage magnitude of 247mV

into a 100Ω load when enabled.

The intended application of this device and

signalling technique is for point-to-point baseband

data transmission over controlled impedance

media approximately 100Ω. The transmission

media may be printed circuit board traces,

backplanes or cables. The ultimate rate and

distance of data transfer is dependent upon the

attenuation characteristics of the media and noise

coupling to the environment.

The STLVDS3487 is characterized for operation

from -40°C to 85°C.

Package

SO-16 (Tube)

SO-16 (Tape & Reel)

TSSOP16 (Tape & Reel)

Comments

50parts per tube / 20tube per box

2500 parts per reel

May 2003

1/13

STLVDS3487

PIN CONFIGURATION

PIN DESCRIPTION

PlN N°

1, 7, 9, 15

2, 6, 10, 14

3, 5, 11, 13

SYMBOL

1A to 4A

1Y to 4Y

1Z to 4Z

1EN, 2EN

3EN, 4EN

GND

NAME AND FUNCTION

Driver Inputs

Driver Outputs

Drivers 1 and 2 Enable

Drivers 3 and 4 Enable

Ground

Supply Voltage

LOGIC DIAGRAM AND LOGIC SYMBOL

2/13

STLVDS3487

TRUTH TABLE

INPUT

OPEN

ENABLES

OUTPUTS

L=Low level, H=High Level, X=Don’t care, Z= High Impedance

ABSOLUTE MAXIMUM RATINGS

Symbol

stg

Supply Voltage (Note 1)

DC Input Voltage

Storage Temperature Range

Parameter

Value

-0.5 to 4.6

-0.5 to (V

+ 0.5)

-65 to +150

Unit

°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is

not implied.

Note 1: All voltages except differential I/O bus voltage, are with respect to the network ground terminal.

RECOMMENDED OPERATING CONDITIONS

Symbol

ILI

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

Operating Temperature Range

-40

Parameter

Min.

3.0

2.0

0.8

Typ.

3.3

Max.

3.6

Unit

°C

3/13

STLVDS3487

ELECTRICAL CHARACTERISTICS

(Over recommended operating conditions unless otherwise noted.

All typical values are at T

= 25°C, and V

= 3.3V)

Symbol

∆V

OC(SS)

Parameter

Differential Output Voltage

Change in Differential

Output Voltage Between

Logic State

Change in Steady-state

Common Mode Output

Voltage Between Logic

State

Steady-state Common

Mode Output Voltage

Peak to Peak Common

mode Output Voltage

Supply Current

= 100Ω

Test Conditions

Fig. 2

Min.

247

-50

Typ.

350

Max.

454

Unit

Fig. 3

1.125

1.2

1.375

OC(SS)

OC(PP)

Fig. 3

-50

150

-24

µA

= 0.8V or 2V, Enabled, No Load

= 0.8V or 2V, Enabled, R

= 100Ω

= 0 or V

, Disabled

11.5

0.3

0.6

6.1

OFF

High Level Input Current

Low Level Input Current

= 2V

= 0.8V

Short Circuit Output Current V

O(Y)

or V

O(Z)

= 0V

= 0

High Impedance Output

Current

Power OFF Output Current

Input Capacitance

= 0 or 2.4V

= 0

= 2.4V

4/13

STLVDS3487

SWITCHING CHARACTERISTICS

(Unless otherwise noted. Typical values are referred to T

= 25°C

and V

= 3.3V)

Symbol

PLH

PHL

sk(P)

sk(O)

PZH

Parameter

Propagation Delay Time,

Low to High Output

Propagation Delay Time,

High to Low Output

Differential Output Signal

Rise Time

Differential Output Signal

Fall Time

Pulse Skew (|t

THL

= t

TLH

= 100Ω

Fig. 2

Test Conditions

= 10pF

Min.

0.5

0.4

Typ.

1.4

1.7

0.5

0.3

5.4

Max.

2.5

0.6

0.3

Unit

PZL

PHZ

PLZ

Channel to Channel Output

Skew (note1)

Propagation Delay Time,

Fig. 4

High Impedance to High

Level Output

Propagation Delay Time,

High Impedance to Low

Level Output

Propagation Delay Time,

High Level to High

Impedance Output

Propagation Delay Time,

Low Level to High

Impedance Output

2.5

8.1

7.3

Note 1: t

sk(O)

is the maximum delay time difference between drivers on the same device.

Note 2: RS-232 IN to TTL-CMOS OUT (from 50% to 50%)

Figure 1 :

Voltage and Current Definitions

5/13

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