NM93CS06/CS46/CS56/CS66 (MICROWIRE Bus Interface) M256-/1024-/2048-/4096-Bit Serial
EEPROM with Data Protect and Sequential Read
NM93CS06/CS46/CS56/CS66
June 1997
NM93CS06/CS46/CS56/CS66
(MICROWIRE
™
Bus Interface) 256-/1024-/2048-/4096-Bit
Serial EEPROM with Data Protect and Sequential Read
General Description
The NM93CS06/CS46/CS56/CS66 devices are 256/ 1024/
2048/4096 bits, respectively, of CMOS non-volatile electri-
cally erasable memory divided into 16/64/128/ 256 16-bit
registers. Selected registers can be protected against data
modification by programming the Protect Register with the
address of the first register to be protected against data
modification (all registers greater than, or equal to, the se-
lected address are then protected from further change). Ad-
ditionally, this address can be “locked” into the device, mak-
ing all future attempts to change data impossible. These
devices are fabricated using Fairchild Semiconductor
floating-gate CMOS process for high reliability, high endur-
ance and low power consumption. The NM93CSXX Family
is offered in both SO and TSSOP packages for small space
considerations.
The EEPROM interfacing is MICROWIRE compatible pro-
viding simple interfacing to standard microcontrollers and mi-
croprocessors. There are a total of 10 instructions, 5 which
operate on the EEPROM memory, and 5 which operate on
the Protect Register. The memory instructions are READ,
WRITE, WRITE ALL, WRITE ENABLE, and WRITE DIS-
ABLE. The Protect register instructions are PRREAD,
PRWRITE, PRENABLE, PRCLEAR, and PRDISABLE.
Features
n
Write protection in a user defined section of memory
n
Sequential register read
n
Typical active current of 200 µA and standby current of
10 µA
n
No erase required before write
n
Reliable CMOS floating gate technology
n
MICROWIRE compatible serial I/O
n
Self timed write cycle
n
Device status during programming mode
n
40 year data retention
n
Endurance: 10
6
data changes
n
4.5V to 5.5V operation in all modes of operation
n
Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
DS010750-1
© 1997 Fairchild Semiconductor Corporation
DS010750
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PrintDate=1997/07/10 PrintTime=18:23:26 10205 ds010750 Rev. No. 3
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Functional Description
The NM93CSxx EEPROM Family has 10 instructions as de-
scribed below. All Data-In signals are clocked into the device
on the low-to-high SK transition.
Read and Sequential Register Read (READ):
The READ instruction outputs serial data on the D0 pin. After
a READ instruction is received, the instruction and address
are decoded, followed by data transfer from the selected
memory register into a 16-bit serial-out shift register. A
dummy bit (logical 0) precedes the 16-bit data output string.
Output data changes are initiated by a low to high transition
of the SK clock. In the
sequential register read
mode of op-
eration, the memory automatically cycles to the next register
after each 16 data bits are clocked out. The dummy-bit is
suppressed in this mode and a continuous string of data is
obtained.
Write Enable (WEN):
When V
CC
is applied to the part, it “powers up” in the Write
Disable (WDS) state. Therefore, all programming modes
must be preceded by a Write Enable (WEN) instruction.
Once a Write Enable instruction is executed, programming
remains enabled until a Write Disable (WDS) instruction is
executed or V
CC
is completely removed from the part.
Write (WRITE):
The WRITE instruction is followed by 16 bits of data to be
written into the specified address. After the last bit of data is
put on the data-in (DI) pin, CS must be brought low before
the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. The PE pin
MUST
be held high while loading the WRITE instruction,
however, after loading the WRITE instruction the PE pin be-
comes a “don’t care”. The D0 pin indicates the READY/
BUSY status of the chip if CS is brought high after the t
CS
in-
terval. D0 = logical 0 indicates that programming is still in
progress. D0 = logical 1 indicates that the register at the ad-
dress specified in the instruction has been written with the
data pattern specified in the instruction and the part is ready
for another instruction.
Write All (WRALL):
The WRALL instruction is valid only when the Protect Regis-
ter has been cleared by executing a PRCLEAR instruction.
The WRALL instruction will simultaneously program all regis-
ters with the data pattern specified in the instruction. Like the
WRITE instruction, the PE pin
MUST
be held high while
loading the WRALL instruction, however, after loading the in-
struction the PE pin becomes a “don’t care”. As in the WRITE
mode, the DO pin indicates the READY/BUSY status of the
chip if CS is brought high after the t
CS
interval. This function
is DISABLED if the Protect Register is in use to lock out a
section of memory.
Write Disable (WDS):
To protect against accidental data disturb, the Write Disable
(WDS) instruction disables all programming modes and
should follow all programming operations. Execution of a
READ instruction is independent of both the WEN and WDS
instructions.
Note:
For all Protect Register Operations: If the PRE pin is
not held at V
IH
, all instructions will be applied to the EE-
PROM array, rather than the Protect Register.
Protect Register Read (PRREAD):
The PRREAD instruction outputs the address stored in the
Protect Register on the DO pin. The PRE pin
MUST
be held
high while loading the instruction sequence. Following the
PRREAD instruction the 6- or 8-bit address stored in the
memory protect register is transferred to the serial out shift
register. As in the READ mode, a dummy bit (logical 0) pre-
cedes the 6- or 8-bit address string.
Protect Register Enable (PREN):
The PREN instruction is used to enable the PRCLEAR,
PRWRITE, and PRDS modes. Before the PREN mode can
be entered, the part must be in the Write Enable (WEN)
mode. Both the PRE and PE pins
MUST
be held high while
loading the instruction sequence.
Note that a PREN instruction must
immediately
precede a
PRCLEAR, PRWRITE, or PRDS instruction.
Protect Register Clear (PRCLEAR):
The PRCLEAR instruction clears the address stored in the
Protect Register and, therefore, enables
all
registers for the
WRITE and WRALL instruction. The PRE and PE pins
must
be held high while loading the instruction sequence, how-
ever, after loading the PRCLEAR instruction the PRE and
PE pins become “don’t care”. Note that a PREN instruction
must
immediately
precede a PRCLEAR instruction.
Please note that the PRCLEAR instruction and the
PRWRITE instruction will both program the Protect Register
with all 1s. However, the PRCLEAR instruction will allow the
LAST register to be programmed, whereas the PRWRITE in-
struction = all 1s will PREVENT the last register from being
programmed. In addition, the PRCLEAR instruction will allow
the use of the WRALL command, where the PRWRITE = all
1s will lock out the Bulk programming opcode.
Protect Register Write (PRWRITE):
The PRWRITE instruction is used to write into the Protect
Register the address of the first register to be protected. Af-
ter the PRWRITE instruction is executed, all memory regis-
ters whose addresses are greater than or equal to the ad-
dress specified in the Protect Register are protected from the
WRITE operation. Note that before executing a PRWRITE
instruction the Protect Register must first be cleared by ex-
ecuting a PRCLEAR operation and that the PRE and PE
pins
must
be held high while loading the instruction, how-
ever, after loading the PRWRITE instruction the PRE and PE
pins become
″don’t
care’. Note that a PREN instruction must
immediately
precede a PRWRITE instruction.
Protect Register Disable (PRDS):
The PRDS instruction is a
ONE
TIME ONLY instruction
which renders the Protect Register unalterable in the future.
Therefore, the specified registers become
PERMANENTLY
protected against data changes. As in the PRWRITE instruc-
tion the PRE and PE pins
must
be held high while loading
the instruction, and after loading the PRDS instruction the
PRE and PE pins become “don’t care”.
Note that a PREN instruction must
immediately
precede a
PRDS instruction.
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