MT46H128M32L2KQ-6IT:A datasheet, PDF

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MT46H128M32L2KQ-6IT:A: DescriptionDDR DRAM, 128MX32, 5ns, CMOS, PBGA168, 12 X 12 MM, GREEN, PLASTIC, WFBGA-168; Categorystorage storage; File Size3MB，106 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT46H128M32L2KQ-6IT:A Overview

DDR DRAM, 128MX32, 5ns, CMOS, PBGA168, 12 X 12 MM, GREEN, PLASTIC, WFBGA-168

MT46H128M32L2KQ-6IT:A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	BGA
package instruction	VFBGA, BGA168,23X23,20
Contacts	168
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
interleaved burst length	2,4,8,16
JESD-30 code	S-PBGA-B168
JESD-609 code	e1
length	12 mm
memory density	4294967296 bit
Memory IC Type	DDR DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	168
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA168,23X23,20
Package shape	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	0.75 mm
self refresh	YES
Continuous burst length	2,4,8,16
Maximum standby current	0.00001 A
Maximum slew rate	0.14 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	12 mm

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2Gb: x16, x32 Mobile LPDDR SDRAM

Features

Mobile Low-Power DDR SDRAM

MT46H128M16LF – 32 Meg x 16 x 4 Banks

MT46H64M32LF – 16 Meg x 32 x 4 Banks

MT46H128M32L2 – 16 Meg x 32 x 4 Banks x 2

MT46H256M32L4 – 32 Meg x 16 x 4 Banks x 4

MT46H256M32R4 – 32 Meg x 16 x 4 Banks x 4

Features

• V

DDQ

= 1.70–1.95V

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• 4 internal banks for concurrent operation

• Data masks (DM) for masking write data; one mask

per byte

• Programmable burst lengths (BL): 2, 4, 8, or 16

• Concurrent auto precharge option is supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS-compatible inputs

• Temperature-compensated self refresh (TCSR)

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• Status read register (SRR)

• Selectable output drive strength (DS)

• Clock stop capability

• 64ms refresh; 32ms for the automotive temperature

range

Table 1: Key Timing Parameters (CL = 3)

Speed Grade

-5

-54

-6

-75

Clock Rate

200 MHz

185 MHz

166 MHz

133 MHz

Access Time

5.0ns

6.0ns

Options

• V

DDQ

– 1.8V/1.8V

• Configuration

– 128 Meg x 16 (32 Meg x 16 x 4

banks)

– 64 Meg x 32 (16 Meg x 32 x 4

banks)

• Addressing

– JEDEC-standard

– Reduced page-size

– 4-die stack reduced page-size

– 2-die stack standard

– 4-die stack standard

• Plastic "green" package

– 60-ball VFBGA (10mm x 11.5mm)

– 90-ball VFBGA (10mm x 13mm)

• PoP (plastic "green" package)

– 168-ball VFBGA (12mm x 12mm)

– 168-ball WFBGA (12mm x 12mm)

– 240-ball WFBGA (14mm x 14mm)

• Timing – cycle time

– 5ns @ CL = 3 (200 MHz)

– 5.4ns @ CL = 3 (185 MHz)

– 6ns @ CL = 3 (166 MHz)

– 7.5ns @ CL = 3 (133 MHz)

• Power

– Standard I

DD2

DD6

• Operating temperature range

– Commercial (0˚ to +70˚C)

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

• Design revision

Notes:

Marking

128M16

64M32

-5

-54

-6

-75

None

Contact factory for availability.

Available in the 168-ball JV package only.

Available only for x16 configuration.

Available only for x32 configuration.

PDF: 09005aef83a73286

2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb: x16, x32 Mobile LPDDR SDRAM

Features

Contents

General Description ......................................................................................................................................... 8

Functional Block Diagrams ............................................................................................................................... 9

Ball Assignments ............................................................................................................................................ 11

Ball Descriptions ............................................................................................................................................ 15

Package Block Diagrams ................................................................................................................................. 17

Package Dimensions ....................................................................................................................................... 20

Electrical Specifications .................................................................................................................................. 26

Electrical Specifications – I

Parameters ........................................................................................................ 29

Electrical Specifications – AC Operating Conditions ......................................................................................... 35

Output Drive Characteristics ........................................................................................................................... 40

Functional Description ................................................................................................................................... 43

Commands .................................................................................................................................................... 44

DESELECT ................................................................................................................................................. 45

NO OPERATION ......................................................................................................................................... 45

LOAD MODE REGISTER ............................................................................................................................. 45

ACTIVE ...................................................................................................................................................... 45

READ ......................................................................................................................................................... 46

WRITE ....................................................................................................................................................... 47

PRECHARGE .............................................................................................................................................. 48

BURST TERMINATE ................................................................................................................................... 49

AUTO REFRESH ......................................................................................................................................... 49

SELF REFRESH ........................................................................................................................................... 50

DEEP POWER-DOWN ................................................................................................................................. 50

Truth Tables ................................................................................................................................................... 51

State Diagram ................................................................................................................................................ 56

Initialization .................................................................................................................................................. 57

Standard Mode Register .................................................................................................................................. 60

Burst Length .............................................................................................................................................. 61

Burst Type .................................................................................................................................................. 61

CAS Latency ............................................................................................................................................... 62

Operating Mode ......................................................................................................................................... 63

Extended Mode Register ................................................................................................................................. 64

Temperature-Compensated Self Refresh ...................................................................................................... 64

Partial-Array Self Refresh ............................................................................................................................ 65

Output Drive Strength ................................................................................................................................ 65

Status Read Register ....................................................................................................................................... 66

Bank/Row Activation ...................................................................................................................................... 68

READ Operation ............................................................................................................................................. 69

WRITE Operation ........................................................................................................................................... 80

PRECHARGE Operation .................................................................................................................................. 92

Auto Precharge ............................................................................................................................................... 92

Concurrent Auto Precharge ......................................................................................................................... 93

AUTO REFRESH Operation ............................................................................................................................. 98

SELF REFRESH Operation ............................................................................................................................... 99

Power-Down ................................................................................................................................................. 100

Deep Power-Down .................................................................................................................................... 102

Clock Change Frequency ............................................................................................................................... 104

Revision History ............................................................................................................................................ 105

Rev. M – 11/10 ........................................................................................................................................... 105

Rev. L – 09/10 ............................................................................................................................................ 105

PDF: 09005aef83a73286

2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb: x16, x32 Mobile LPDDR SDRAM

Features

List of Figures

Figure 1: 2Gb Mobile LPDDR Part Numbering .................................................................................................. 2

Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9

Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10

Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 11

Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 12

Figure 6: 168-Ball FBGA – 12mm x 12mm (Top View), x32 only ........................................................................ 13

Figure 7: 240-Ball FBGA – 14mm x 14mm (Top View), x32 only ........................................................................ 14

Figure 8: Single Rank, Single Channel (1 Die) Package Block Diagram .............................................................. 17

Figure 9: Dual Rank, Single Channel (2 Die) Package Block Diagram ................................................................ 18

Figure 10: Dual Rank, Single Channel (4 Die) Package Block Diagram .............................................................. 19

Figure 11: 60-Ball VFBGA (10mm x 11.5mm), Package Code: CK ...................................................................... 20

Figure 12: 90-Ball VFBGA (10mm x 13mm), Package Code: CM ........................................................................ 21

Figure 13: 168-Ball VFBGA (12mm x 12mm), Package Code: JV ........................................................................ 22

Figure 14: 168-Ball WFBGA (12mm x 12mm), Package Code: KQ ...................................................................... 23

Figure 15: 168-Ball WFBGA (12mm x 12mm), Package Code: MA ..................................................................... 24

Figure 16: 240-Ball WFBGA (14mm x 14mm), Package Code: MC ..................................................................... 25

Figure 17: Typical Self Refresh Current vs. Temperature .................................................................................. 34

Figure 18: ACTIVE Command ........................................................................................................................ 46

Figure 19: READ Command ........................................................................................................................... 47

Figure 20: WRITE Command ......................................................................................................................... 48

Figure 21: PRECHARGE Command ................................................................................................................ 49

Figure 22: DEEP POWER-DOWN Command ................................................................................................... 50

Figure 23: Simplified State Diagram ............................................................................................................... 56

Figure 24: Initialize and Load Mode Registers ................................................................................................. 58

Figure 25: Alternate Initialization with CKE LOW ............................................................................................ 59

Figure 26: Standard Mode Register Definition ................................................................................................. 60

Figure 27: CAS Latency .................................................................................................................................. 63

Figure 28: Extended Mode Register ................................................................................................................ 64

Figure 29: Status Read Register Timing ........................................................................................................... 66

Figure 30: Status Register Definition .............................................................................................................. 67

Figure 31: READ Burst ................................................................................................................................... 70

Figure 32: Consecutive READ Bursts .............................................................................................................. 71

Figure 33: Nonconsecutive READ Bursts ........................................................................................................ 72

Figure 34: Random Read Accesses .................................................................................................................. 73

Figure 35: Terminating a READ Burst ............................................................................................................. 74

Figure 36: READ-to-WRITE ............................................................................................................................ 75

Figure 37: READ-to-PRECHARGE .................................................................................................................. 76

Figure 38: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x16) .................................................... 77

Figure 39: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x32) .................................................... 78

Figure 40: Data Output Timing –

AC and

DQSCK .......................................................................................... 79

Figure 41: Data Input Timing ......................................................................................................................... 81

Figure 42: Write – DM Operation .................................................................................................................... 82

Figure 43: WRITE Burst ................................................................................................................................. 83

Figure 44: Consecutive WRITE-to-WRITE ....................................................................................................... 84

Figure 45: Nonconsecutive WRITE-to-WRITE ................................................................................................. 84

Figure 46: Random WRITE Cycles .................................................................................................................. 85

Figure 47: WRITE-to-READ – Uninterrupting ................................................................................................. 86

Figure 48: WRITE-to-READ – Interrupting ...................................................................................................... 87

Figure 49: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 88

Figure 50: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 89

PDF: 09005aef83a73286

2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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