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MT9VDVF3272G-265XX

Description
DDR DRAM Module, 32MX72, 0.75ns, CMOS, DIMM-184
Categorystorage    storage   
File Size596KB,39 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT9VDVF3272G-265XX Overview

DDR DRAM Module, 32MX72, 0.75ns, CMOS, DIMM-184

MT9VDVF3272G-265XX Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMicron Technology
Parts packaging codeDIMM
package instructionDIMM,
Contacts184
Reach Compliance Codecompliant
ECCN codeEAR99
access modeSINGLE BANK PAGE BURST
Maximum access time0.75 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N184
memory density2415919104 bit
Memory IC TypeDDR DRAM MODULE
memory width72
Number of functions1
Number of ports1
Number of terminals184
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX72
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)235
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal locationDUAL
Maximum time at peak reflow temperature30
256MB, 512MB: (x72, SR) 184-Pin DDR VLP RDIMM
Features
DDR SDRAM VLPRegistered DIMM
MT9VDVF3272 – 256MB
MT9VDVF6472 – 512MB
For the corresponding component data sheet, go to Micron’s Web site:
www.micron.com/modules
Features
• 184-pin, very low profile dual in-line memory
module (VLP DIMM)
• Fast data transfer rates: PC1600, PC2100, or PC2700
• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR
SDRAM components
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Supports ECC error detection and correction
• 256MB (32 Meg x 72); and 512MB (64 Meg x 72)
• V
DD
= V
DDQ
= +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes
• 7.8125µs maximum average periodic refresh
interval
• Serial presence-detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
Figure 1:
184-Pin VLP DIMM (MO-206)
Very Low-Profile 0.72in. (18.29mm)
Options
• Operating temperature range
Commercial (0°C
T
A
+70°C)
Industrial (-40°C
T
A
+85°C)
• Package
184-pin DIMM (standard)
184-pin DIMM (lead-free)
1
• Memory dlock, speed, CAS latency
2
6ns (167 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
10ns (100 MHz), 200 MT/s, CL = 2
• PCB height
Very low-profile 0.72in. (18.30mm)
Marking
none
I
1
G
Y
-335
-262
1
-26A
1
-265
-202
Notes: 1. Contact Micron for product availability.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
PDF: 09005aef81cf6969/Source: 09005aef81cf67b0
DVF9C32_64x72_1.fm - Rev. A 8/05 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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