MT58L64V32FF-6.8 datasheet, PDF

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MT58L64V32FF-6.8: DescriptionStandard SRAM, 64KX32, 6.8ns, CMOS, PBGA165, FBGA-165; Categorystorage storage; File Size484KB，25 Pages; ManufacturerCypress Semiconductor

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MT58L64V32FF-6.8 Overview

Standard SRAM, 64KX32, 6.8ns, CMOS, PBGA165, FBGA-165

MT58L64V32FF-6.8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	TBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	6.8 ns
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	2097152 bit
Memory IC Type	STANDARD SRAM
memory width	32
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX32
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	220
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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2Mb: 128K x 18, 64K x 32/36

FLOW-THROUGH SYNCBURST SRAM

2Mb SYNCBURST

™

SRAM

FEATURES

• Fast clock and OE# access times

• Single +3.3V +0.3V/-0.165V power supply (V

)

• Separate +3.3V or +2.5V isolated output buffer

supply (V

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL

WRITE

• Three chip enables for simple depth expansion and

address pipelining

• Clock-controlled and registered addresses, data

I/Os and control signals

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down

• 100-pin TQFP package

• 165-pin FBGA package

• Low capacitive bus loading

• x18, x32, and x36 versions available

MT58L128L18F, MT58L64L32F,

MT58L64L36F; MT58L128V18F,

MT58L64V32F, MT58L64V36F

3.3V V

, 3.3V or 2.5V I/O, Flow-Through

100-Pin TQFP*

165-Pin FBGA

(Preliminary Package Data)

OPTIONS

• Timing (Access/Cycle/MHz)

6.8ns/8.0ns/125 MHz

7.5ns/8.8ns/113 MHz

8.5ns/10ns/100 MHz

10ns/15ns/66 MHz

• Configurations

3.3V I/O

128K x 18

64K x 32

64K x 36

2.5V I/O

128K x 18

64K x 32

64K x 36

• Packages

100-pin TQFP

165-pin FBGA

• Operating Temperature Range

Commercial (0°C to +70°C)

Part Number Example:

MARKING

-6.8

-7.5

-8.5

-10

MT58L128L18F

MT58L64L32F

MT58L64L36F

MT58L128V18F

MT58L64V32F

MT58L64V36F

None

*JEDEC-standard MS-026 BHA (LQFP).

GENERAL DESCRIPTION

The Micron

SyncBurst

™

SRAM family employs

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

Micron’s 2Mb SyncBurst SRAMs integrate a 128K x

18, 64K x 32, or 64K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single clock

input (CLK). The synchronous inputs include all ad-

dresses, all data inputs, active LOW chip enable (CE#),

MT58L64L36FT-8.5*

*See page 24 for the FBGA Part Marking Guide

2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM

MT58L128L18F_2.p65 – Rev. 8/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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