DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD42S17800, 4217800
16 M-BIT DYNAMIC RAM
2 M-WORD BY 8-BIT, FAST PAGE MODE
Description
The
µ
PD42S17800, 4217800 are 2,097,152 words by 8 bits CMOS dynamic RAMs. The fast page mode capability
realize high speed access and low power consumption.
These differ in refresh cycle and the
µ
PD42S17800 can execute CAS before RAS self refresh.
These are packaged in 28-pin plastic TSOP(II) and 28-pin plastic SOJ.
Features
• 2,097,152 words by 8 bits organization
• Fast page mode
• Fast access and cycle time
Power consumption
Active (MAX.)
605 mW
550 mW
Access time
(MAX.)
60 ns
70 ns
R/W cycle time
(MIN.)
110 ns
130 ns
Fast page mode
cycle time (MIN.)
40 ns
45 ns
• Single +5.0 V
±
10 % power supply
Part number
µ
PD42S17800-60, 4217800-60
µ
PD42S17800-70, 4217800-70
• The
µ
PD42S17800 can execute CAS before RAS self refresh
Power consumption at standby
(MAX.)
1.4 mW
(CMOS level input)
5.5 mW
(CMOS level input)
Part number
Refresh cycle
2,048 cycles/128 ms
Refresh
CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh
CAS before RAS refresh,
RAS only refresh,
Hidden refresh
µ
PD42S17800
µ
PD4217800
2,048 cycles/32 ms
The information in this document is subject to change without notice.
Document No. IC-3190.CU1
1
©
1995
µ
PD42S17800, 4217800
Ordering Information
Part number
Access time
(MAX.)
60 ns
70 ns
60 ns
70 ns
60 ns
70 ns
60 ns
70 ns
Package
28-pin Plastic TSOP (II)
(400 mil)
28-pin Plastic SOJ
(400 mil)
28-pin Plastic TSOP (II)
(400 mil)
28-pin Plastic SOJ
(400 mil)
Refresh
CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh
µ
PD42S17800G5-60
µ
PD42S17800G5-70
µ
PD42S17800LE-60
µ
PD42S17800LE-70
µ
PD4217800G5-60
µ
PD4217800G5-70
µ
PD4217800LE-60
µ
PD4217800LE-70
2
µ
PD42S17800, 4217800
Pin Configurations
(Marking Side)
28-pin Plastic TSOP (II) (400 mil)
28-pin Plastic SOJ (400 mil)
V
CC
I/O1
I/O2
I/O3
I/O4
WE
RAS
NC
A10
A0
A1
A2
A3
V
CC
1
2
3
4
28
27
26
25
GND
I/O8
I/O7
I/O6
I/O5
CAS
OE
A9
A8
A7
A6
A5
A4
GND
V
CC
I/O1
I/O2
I/O3
I/O4
WE
RAS
NC
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
28
27
26
25
24
GND
I/O8
I/O7
I/O6
I/O5
CAS
OE
A9
A8
A7
A6
A5
A4
GND
µ
PD42S17800G
µ
PD4217800G5
5
6
7
8
9
10
11
12
13
14
24
23
22
21
20
19
18
17
16
15
µ
PD42S17800LE
µ
PD4217800LE
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
A0 to A10
RAS
CAS
WE
OE
V
CC
GND
NC
: Address inputs
: Row address strobe
: Column address strobe
: Write enable
: Output enable
: Power Supply
: Ground
: No connection
I/O1 to I/O8 : Data Inputs/Outputs
3
µ
PD42S17800, 4217800
Block Diagram
RAS
CAS
WE
Data
Output
Buffer
Clock
Generator
OE
V
CC
GND
CAS before
RAS Counter
Row Decoder
Memory
Cell
Array
Bit organization
Note2
I/O1
to
I/O8
Row
Address
Buffer
Address
Note 1
Column
Address
Buffer
Column Decoder
Sense Amplifier
×
8
Data
Input
Buffer
Notes 1.
Part number
Row address
A0 – A10
Column address
A0 – A9
µ
PD42S17800, 4217800
2.
µ
PD42S17800, 4217800...2,048×1,024×8
4
µ
PD42S17800, 4217800
Input/Output Pin Functions
The
µ
PD42S17800, 4217800 have input pins RAS, CAS, WE, OE, Address
Note
and input/output pins
I/O1 to I/O8.
Pin name
RAS
(Row address strobe)
Input/Output
Input
Function
RAS activates the sense amplifier by latching a row address and select-
ing a corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh
CAS
(Column address strobe)
A0 to A×
Note
(Address inputs)
Input
CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.
Address bus.
Input total 21-bit of address signal, upper bits and lower bits
Note
in
sequence (address multiplex method).
Therefore, one word is selected from 2,097,152-word by 8-bit memory
cell array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (t
ASR
, t
ASC
) and hold time (t
RAH
,
t
CAH
) are specified for the activation of RAS and CAS.
Write control signal.
Write operation is executed by activating RAS, CAS and WE.
Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the
device.
Therefore, read operation cannot be executed.
Input
WE
(Write enable)
OE
(Output enable)
Input
Input
I/O1 to I/O8
(Data inputs/outputs)
Input/Output
8-bit data bus.
I/O1 to I/O8 are used to input/output data.
Note
Part number
Address inputs
A0 – A10
Upper bits
11 bits
Lower bits
10 bits
µ
PD42S17800, 4217800
5
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