MT16JSS51264HIY-80CXX datasheet, PDF

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MT16JSS51264HIY-80CXX: DescriptionDDR DRAM Module, 512MX64, CMOS, LEAD FREE, MO-268, SODIMM-204; Categorystorage storage; File Size496KB，18 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT16JSS51264HIY-80CXX Overview

DDR DRAM Module, 512MX64, CMOS, LEAD FREE, MO-268, SODIMM-204

MT16JSS51264HIY-80CXX Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	SODIMM
package instruction	LEAD FREE, MO-268, SODIMM-204
Contacts	204
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N204
JESD-609 code	e4
length	67.6 mm
memory density	34359738368 bit
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	204
word count	536870912 words
character code	512000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512MX64
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	3.8 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Gold (Au)
Terminal form	NO LEAD
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	30 mm

MT16JSS51264HIY-80CXX Preview

4GB (x64, DR): 204-Pin DDR3 SDRAM SODIMM

Features

DDR3 SDRAM SODIMM

MT16JSS51264H – 4GB

For component data sheets, refer to Micron’s Web site:

www.micron.com

Features

• DDR3 functionality and operations supported as

defined in the component data sheet

• 204-pin, small-outline dual in-line memory module

(SODIMM)

• Fast data transfer rates: PC3-10600, PC3-8500,

or PC3-6400

• 4GB (512 Meg x 64)

• Vdd = 1.5V ±0.075V

• Vddspd = +3.0V to +3.6V

• Nominal and dynamic on-die termination (ODT) for

data and strobe mask signals

• Dual rank, using 4Gb TwinDie™ DRAM

• On-board I

C temperature sensor with integrated

serial presence-detect (SPD) EEPROM

• Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

• Selectable BC4 or BL8 on-the-fly (OTF)

• Gold edge contacts

• Lead-free

• Fly-by topology

• Terminated control, command, and address bus

Figure 1:

204-Pin SODIMM (MO-268 R/C D)

PCB height: 30.0mm (1.18in)

Options

•

–

Commercial (0°C

≤

+70°C)

–

Industrial (–40°C

≤

+85°C)

• Package

–

204-pin DIMM (lead-free)

• Frequency/CAS latency

–

1.5ns @ CL = 8 (DDR3-1333)

–

1.5ns @ CL = 9 (DDR3-1333)

–

1.5ns @ CL = 10 (DDR3-1333)

–

1.87ns @ CL = 7 (DDR3-1066)

–

1.87ns @ CL = 8 (DDR3-1066)

–

2.5ns @ CL = 5 (DDR3-800)

–

2.5ns @ CL = 6 (DDR3-800)

Operating temperature

Marking

None

-1G5

-1G4

-1G3

-1G1

-1G0

-80C

-80B

Notes: 1. Contact Micron for industrial temperature

module offerings.

2. Not recommended for new designs.

Table 1:

Speed

Grade

-1G5

-1G4

-1G3

-1G1

-1G0

-80C

-80B

Key Timing Parameters

Industry

Nomenclature

PC3-10600

PC3-8500

PC3-6400

Data Rate (MT/s)

CL = 10

1333

–

CL = 9

1333

–

CL = 8

1333

1066

–

CL = 7

1066

–

1066

–

CL = 6

800

CL = 5

800

–

800

–

RCD

(ns)

13.5

13.125

12.5

(ns)

49.5

50.625

52.5

13.5

13.125

12.5

PDF: 09005aef832ed836/Source: 09005aef832ed8fb

JSS16C512x64H.fm - Rev. B 12/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

4GB (x64, DR): 204-Pin DDR3 SDRAM SODIMM

Features

Table 2:

Parameter

Refresh count

Row address

Device bank address

Device configuration

Column address

Module rank address

Addressing

4GB

32K A[14:0]

8 BA[2:0]

4Gb TwinDie (512 Meg x 8)

1K A[9:0]

2 S#[1:0]

Table 3:

Part Numbers and Timing Parameters – 4GB Modules

Base device: MT41J512M8THU,

4Gb TwinDie DDR3 SDRAM

Module

Density

4GB

Module

Bandwidth

10.6 GB/s

8.5 GB/s

6.4 GB/s

Memory Clock/

Data Rate

1.5ns/1333 MT/s

1.87ns/1066 MT/s

2.5ns/800 MT/s

Clock Cycles

(CL-

RCD-

RP)

8-8-8

9-9-9

10-10-10

7-7-7

8-8-8

5-5-5

6-6-6

Part Number

Configuration

512 Meg x 64

MT16JSS51264H(I)Y-1G5__

MT16JSS51264H(I)Y-1G4__

MT16JSS51264H(I)Y-1G3__

MT16JSS51264H(I)Y-1G1__

MT16JSS51264H(I)Y-1G0__

MT16JSS51264H(I)Y-80C__

MT16JSS51264H(I)Y-80B__

Notes:

1. The data sheet for the base device can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and

PCB revisions. Consult factory for current revision codes. Example: MT16JSS51264HY-1G1D1.

PDF: 09005aef832ed836/Source: 09005aef832ed8fb

JSS16C512x64H.fm - Rev. B 12/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4GB (x64, DR): 204-Pin DDR3 SDRAM SODIMM

Pin Assignments and Descriptions

Table 4:

Pin Assignments

204-Pin DDR3 SODIMM Front

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

Vrefdq

Vss

DQ0

DQ1

Vss

DM0

Vss

DQ2

DQ3

Vss

DQ8

DQ9

Vss

DQS1#

DQS1

Vss

DQ10

DQ11

Vss

DQ16

DQ17

Vss

DQS2#

DQS2

Vss

DQ18

101

103

DQ19

Vss

DQ24

DQ25

Vss

DM3

Vss

DQ26

DQ27

Vss

CKE0

Vdd

BA2

Vdd

A12

Vdd

CK0

CK0#

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

Vdd

A10

BA0

Vdd

WE#

CAS#

Vdd

A13

S1#

Vdd

Vss

DQ32

DQ33

Vss

DQS4#

DQS4

Vss

DQ34

DQ35

Vss

DQ40

DQ41

Vss

DM5

Vss

157 DQ42

159 DQ43

161

Vss

163 DQ48

165 DQ49

167

Vss

169 DQS6#

171 DQS6

173

Vss

175 DQ50

177 DQ51

179

Vss

181 DQ56

183 DQ57

185

Vss

187

DM7

189

Vss

191 DQ58

193 DQ59

195

Vss

197

SA0

199 Vddspd

201

SA1

203

Vtt

204-Pin DDR3 SODIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

Vss

DQ4

DQ5

Vss

DQS0#

DQS0

Vss

DQ6

DQ7

Vss

DQ12

DQ13

Vss

DM1

RESET#

Vss

DQ14

DQ15

Vss

DQ20

DQ21

Vss

DM2

Vss

DQ22

DQ23

100

102

104

Vss

DQ28

DQ29

Vss

DQS3#

DQS3

Vss

DQ30

DQ31

Vss

CKE1

Vdd

A14

Vdd

A11

Vdd

CK1

CK1#

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

Vdd

BA1

RAS#

Vdd

S0#

ODT0

Vdd

ODT1

Vdd

Vrefca

Vss

DQ36

DQ37

Vss

DM4

Vss

DQ38

DQ39

Vss

DQ44

DQ45

Vss

DQS5#

DQS5

Vss

158 DQ46

160 DQ47

162

Vss

164 DQ52

166 DQ53

168

Vss

170

DM6

172

Vss

174 DQ54

176 DQ55

178

Vss

180 DQ60

182 DQ61

184

Vss

186 DQS7#

188

DQS7

190

Vss

192 DQ62

194 DQ63

196

Vss

198 EVENT#

200

SDA

202

SCL

204

Vtt

PDF: 09005aef832ed836/Source: 09005aef832ed8fb

JSS16C512x64H.fm - Rev. B 12/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4GB (x64, DR): 204-Pin DDR3 SDRAM SODIMM

Pin Assignments and Descriptions

Table 5:

Symbol

A[14:0]

Pin Descriptions

Type

Input

Description

BA[2:0]

CK[1:0],

CK#[1:0]

CKE[1:0]

DM[7:0]

ODT[1:0]

RAS#, CAS#,

WE#

RESET#

S#[1:0]

SA[1:0]

SCL

DQ[63:0]

DQS[7:0],

DQS#[7:0]

SDA

EVENT#

Vdd

Vddspd

Vrefca

Vrefdq

Vss

Vtt

Address inputs:

Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 is sampled during a PRECHARGE

command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank

selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the

bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”

during CAS commands. The address inputs also provide the op-code during the mode

Input

Bank address inputs:

BA[2:0] define the device bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register

(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.

Input

Clock:

CK and CK# are differential clock inputs. All control, command, and address input

signals are sampled on the crossing of the positive edge of CK and the negative edge of

CK#.

Input

Clock enable:

CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM.

Input

Input data mask:

DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH, along with the input data, during a write access. DM is sampled on

both edges of the DQS. Although the DM pins are input-only, the DM loading is designed

to match that of the DQ and DQS pins.

Input

On-die termination:

ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DRAM. When enabled in normal operation, ODT is

only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be

ignored if disabled via the LOAD MODE command.

Input

Command inputs:

RAS#, CAS#, and WE# (along with S#) define the command being

entered.

Input

Reset:

RESET# is an active LOW CMOS input referenced to Vss.The RESET# input receiver is

(LVCMOS) a CMOS input defined as a rail-to-rail signal with DC HIGH

≥

0.8 × Vdd and DC LOW

≤

0.2 × Vdd.

Input

Chip select:

S# enables (registered LOW) and disables (registered HIGH) the command

decoder.

Input

Serial address inputs:

These pins are used to configure the temperature sensor/SPD

EEPROM address range on the I

C bus.

Input

Serial clock for temperature sensor/SPD EEPROM:

SCL is used to synchronize

communication to and from the temperature sensor/SPD EEPROM.

I/O

Data input/output:

Bidirectional data bus.

I/O

Data strobe:

DQS and DQS# are differential data strobes. Output with read data. Edge-

aligned with read data. Input with write data. Center-aligned with write data.

I/O

Serial data:

SDA is a bidirectional pin used to transfer addresses and data into and out of

the temperature sensor/SPD EEPROM on the module on the I

C bus.

Output

Temperature event:

The EVENT# pin is asserted by the temperature sensor when critical

(open drain) temperature thresholds have been exceeded.

Supply

Power supply:

1.5V ±0.075V. The component Vdd and Vddq are connected to the

module Vdd.

Supply

Temperature sensor/SPD EEPROM power supply:

+3.0V to +3.6V.

Supply

Reference voltage:

Control, command, and address (Vdd/2).

Supply

Reference voltage:

DQ, DM (Vdd/2).

Supply

Ground.

Supply

Termination voltage:

Used for control, command, and address (Vdd/2).

–

No connect:

These pins are not connected on the module.

Micron Technology, Inc., reserves the right to change products or specifications without notice.

PDF: 09005aef832ed836/Source: 09005aef832ed8fb

JSS16C512x64H.fm - Rev. B 12/08 EN

4GB (x64, DR): 204-Pin DDR3 SDRAM SODIMM

Functional Block Diagram

Figure 2:

S1#

S0#

DQS0#

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQ

DQS#

CS# DQ

DQS#

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

Functional Block Diagram

DQS4#

DQS4

DM4

DM CS# DQ

DQS#

DM CS# DQ

DQS#

U1b

U1t

U3b

U3t

Vss

DQS1#

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CS# DQ

DQS#

CS# DQ

DQS#

DQS5#

DQS5

DM5

DM CS# DQ

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS#

DM CS# DQ

DQS#

Vss

U9b

U9t

U7b

U7t

Vss

DQS2#

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

CS# DQ

DQS#

CS# DQ

DQS#

DQS6#

DQS6

DM6

DM CS# DQ

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS#

DM CS# DQ

DQS#

Vss

U2b

U2t

U4b

U4t

Vss

DQS3#

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

CS# DQ

DQS#

CS# DQ

DQS#

DQS7#

DQS7

DM7

DM CS# DQ

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS#

DM CS# DQ

DQS#

Vss

U8b

U8t

U6b

U6t

Vss

Rank 0 = U1b–U4b, U6b–U9b

Rank 1 = U1t–U4t, U6t–U9t

BA[2:0]

A[14:0]

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

RESET#

BA[2:0]:

DDR3 SDRAM

A[14:0]:

DDR3 SDRAM

RAS#: DDR3 SDRAM

CAS#: DDR3 SDRAM

WE#: DDR3 SDRAM

CKE0: Rank 0

CKE1: Rank 1

ODT0: Rank 0

ODT1: Rank 1

RESET#: DDR3 SDRAM

U10

SCL

Temperature

sensor/

SPD EEPROM

EVT A0

A1 A2

SA0 SA1 Vss

SDA

CK0

CK0#

CK1

CK1#

Rank 0

Rank 1

EVENT#

ddspd

ref

SPD EEPROM

DDR3 SDRAM

Clock, command, control, and address line terminations:

S#[1:0], CKE[1:0], A[14:0],

RAS#, CAS#, WE#,

ODT[1:0], BA[2:0]

DDR3

SDRAM

DDR3

SDRAM

CK#

Notes:

1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor that is

tied to ground. It is used for the calibration of the component’s ODT and output driver.

PDF: 09005aef832ed836/Source: 09005aef832ed8fb

JSS16C512x64H.fm - Rev. B 12/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology
Parts packaging code	SODIMM	SODIMM	SODIMM	SODIMM	SODIMM	SODIMM	SODIMM	SODIMM	SODIMM	SODIMM
package instruction	LEAD FREE, MO-268, SODIMM-204	DIMM,	LEAD FREE, MO-268, SODIMM-204	LEAD FREE, MO-268, SODIMM-204	LEAD FREE, MO-268, SODIMM-204	DIMM,	DIMM,	LEAD FREE, MO-268, SODIMM-204	LEAD FREE, MO-268, SODIMM-204	LEAD FREE, MO-268, SODIMM-204
Contacts	204	204	204	204	204	204	204	204	204	204
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N204	R-XDMA-N204	R-XDMA-N204	R-XDMA-N204	R-XDMA-N204	R-XDMA-N204	R-XDMA-N204	R-XDMA-N204	R-XDMA-N204	R-XDMA-N204
JESD-609 code	e4	e4	e4	e4	e4	e4	e4	e4	e4	e4
length	67.6 mm	67.6 mm	67.6 mm	67.6 mm	67.6 mm	67.6 mm	67.6 mm	67.6 mm	67.6 mm	67.6 mm
memory density	34359738368 bit	34359738368 bit	34359738368 bit	34359738368 bit	34359738368 bit	34359738368 bit	34359738368 bit	34359738368 bit	34359738368 bit	34359738368 bit
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	64	64	64	64	64	64	64	64	64	64
Number of functions	1	1	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1	1	1
Number of terminals	204	204	204	204	204	204	204	204	204	204
word count	536870912 words	536870912 words	536870912 words	536870912 words	536870912 words	536870912 words	536870912 words	536870912 words	536870912 words	536870912 words
character code	512000000	512000000	512000000	512000000	512000000	512000000	512000000	512000000	512000000	512000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	70 °C	70 °C	85 °C	85 °C	70 °C	85 °C	85 °C	70 °C	70 °C
organize	512MX64	512MX64	512MX64	512MX64	512MX64	512MX64	512MX64	512MX64	512MX64	512MX64
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260	260	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.8 mm	3.8 mm	3.8 mm	3.8 mm	3.8 mm	3.8 mm	3.8 mm	3.8 mm	3.8 mm	3.8 mm
self refresh	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V
Minimum supply voltage (Vsup)	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V
Nominal supply voltage (Vsup)	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
surface mount	NO	NO	NO	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Gold (Au)	Gold (Au)	Gold (Au)	Gold (Au)	Gold (Au)	Gold (Au)	Gold (Au)	Gold (Au)	Gold (Au)	Gold (Au)
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30	30	30	30	30	30
width	30 mm	30 mm	30 mm	30 mm	30 mm	30 mm	30 mm	30 mm	30 mm	30 mm

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