K4D261638F
128M GDDR SDRAM
128Mbit GDDR SDRAM
Revision 1.5
March 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev 1.5 (Mar. 2005)
K4D261638F
Revision History
Revision 1. 5(March 17, 2005)
• Added Full output driver impedance in the EMRS spec.
128M GDDR SDRAM
Revision 1. 4 (February 2, 2005)
• Added -TC5A speed in the spec
Revision 1.3 (November 2, 2004)
• Added ns scale based AC spec table.
• Removed -TC25 from the spec
Revision 1.2 (January 30, 2004)
• Changed tWR & tWR_A of K4D261638F-TC25/2A/33/36 from 3tCK to 4tCK
• Changed tRC of K4D261638F-TC25 from 17tCK to 18tCK
• Changed tRC of K4D261638F-TC2A/33/36 from 15tCK to 16tCK
• Changed tRAS of K4D261638F-TC25 from 12tCK to 13tCK.
• Changed tRAS of K4D261638F-TC2A/33/36 from 10tCK to 11tCK.
• Changed tDAL of K4D261638F-TC25/2A/33/36 from 8tCK to 9tCK
Revision 1.1 (January 7, 2004)
• Added K4D261638F-TC25 in the spec.
Revision 1.0 (December 5, 2003)
Revision 0.9 (October 14, 2003) -
Preliminary Spec
• Defined DC spec
Revision 0.1 (October 2, 2003) -
Target Spec
• Added Lead free package part number in the datasheet
Revision 0.0 (August 6, 2003) -
Target Spec
• Defined Target Specification
- 2 -
Rev 1.5 (Mar. 2005)
K4D261638F
128M GDDR SDRAM
2M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 2.5V + 5% power supply for device operation
• 2.5V + 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3, 4 and 5(clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 2 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 66pin TSOP-II
• Maximum clock frequency up to 350MHz
• Maximum data rate up to 700Mbps/pin
ORDERING INFORMATION
Part NO.
K4D261638F-TC2A
K4D261638F-TC33
K4D261638F-TC36
K4D261638F-TC40
K4D261638F-TC50
K4D261638F-TC5A
Max Freq.
350MHz
300MHz
275MHz
250MHz
200MHz
200MHz
Max Data Rate
700Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
400Mbps/pin
400Mbps/pin
SSTL_2
66pin TSOP-II
Interface
Package
K4D261638F-LC is the Lead Free package part number.
For the K4D261638F-TC2A, VDD & VDDQ = 2.8V+0.1V
For the K4D261638F-TC5A, VDD & VDDQ = 2.4V to 2.7V
GENERAL DESCRIPTION
FOR 2M x 16Bit x 4 Bank DDR SDRAM
The K4D261638F is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by
16 bits, fabricated with SAMSUNG
’
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev 1.5 (Mar. 2005)
K4D261638F
PIN CONFIGURATION
(Top View)
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CK
CK
CKE
NC
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
128M GDDR SDRAM
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm Pin Pitch)
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
CAS
WE
L(U)DQS
L(U)DM
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA
0
, BA
1
A
0
~A
11
DQ
0
~ DQ
15
V
DD
V
SS
V
DDQ
V
SSQ
NC
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ
’
s
Ground for DQ
’
s
No Connection
- 4 -
Rev 1.5 (Mar. 2005)
K4D261638F
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK, CK*1
Input
Type
128M GDDR SDRAM
Function
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
’
s and DM
’
s that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS
corresponds to the data on DQ8-DQ15.
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on
DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
11
, Column addresses : CA
0
~ CA
8
.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommended to be left "No connection" on the device
CKE
Input
CS
Input
RAS
CAS
WE
Input
Input
Input
LDQS,UDQS
Input/Output
LDM,UDM
DQ
0
~ DQ
15
BA
0
, BA
1
A
0
~ A
11
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
NC/RFU
Input
Input/Output
Input
Input
Power Supply
Power Supply
Power Supply
No connection/
Reserved for future use
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
- 5 -
Rev 1.5 (Mar. 2005)
MCU
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