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MT58L512L18PF-5

Description
Cache SRAM, 512KX18, 3.1ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
Categorystorage    storage   
File Size656KB,32 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT58L512L18PF-5 Overview

Cache SRAM, 512KX18, 3.1ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165

MT58L512L18PF-5 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicron Technology
Parts packaging codeBGA
package instruction13 X 15 MM, FBGA-165
Contacts165
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.A
Maximum access time3.1 ns
I/O typeCOMMON
JESD-30 codeR-PBGA-B165
JESD-609 codee0
length15 mm
memory density9437184 bit
Memory IC TypeCACHE SRAM
memory width18
Number of functions1
Number of terminals165
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTBGA
Encapsulate equivalent codeBGA165,11X15,40
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE
Parallel/SerialPARALLEL
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.01 A
Minimum standby current3.14 V
Maximum slew rate0.525 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width13 mm
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
8Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
DD
)
• Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium
®
BSRAM-compatible)
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
WRITE
• Three chip enables for simple depth expansion
and address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
• Automatic power-down for portable applications
• 100-pin TQFP package
• 165-pin FBGA package
• 119-pin BGA package
• Low capacitive bus loading
• x18, x32, and x36 versions available
MT58L512L18P, MT58L256L32P, MT58L256L36P;
MT58L512V18P, MT58L256V32P, MT58L256V36P
3.3V V
DD
, 3.3V or 2.5V I/O, Pipelined, Single-Cycle
Deselect
100-Pin TQFP
1
165-Pin FBGA
(Preliminary Package Data)
OPTIONS
• Timing (Access/Cycle/MHz)
3.1ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V I/O
512K x 18
256K x 32
256K x 36
2.5V I/O
512K x 18
256K x 32
256K x 36
• Packages
100-pin TQFP (2-chip enable)
100-pin TQFP (3-chip enable)
165-pin, 13mm x 15mm FBGA
119-pin, 14mm x 22mm BGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
MARKING
-5
-6
-7.5
-10
MT58L512L18P
MT58L256L32P
MT58L256L36P
MT58L512V18P
MT58L256V32P
MT58L256V36P
T
S
F*
B
None
IT
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
2. JEDEC-standard MS-028 BHA (PBGA).
119-Pin BGA
2
Part Number Example:
MT58L512L18PT-6
* A Part Marking Guide for the FBGA devices can be found on Micron’s
web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_2.p65 – Rev. 6/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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