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MT48LC16M8A2BB-7EIT

Description
Synchronous DRAM, 16MX8, 5.4ns, CMOS, PBGA60, 8 X 16 MM, LEAD FREE, PLASTIC, FBGA-60
Categorystorage    storage   
File Size2MB,58 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance  
Download Datasheet Parametric View All

MT48LC16M8A2BB-7EIT Overview

Synchronous DRAM, 16MX8, 5.4ns, CMOS, PBGA60, 8 X 16 MM, LEAD FREE, PLASTIC, FBGA-60

MT48LC16M8A2BB-7EIT Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicron Technology
Parts packaging codeBGA
package instructionTFBGA, BGA60,8X15,32
Contacts60
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)143 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PBGA-B60
JESD-609 codee1
length16 mm
memory density134217728 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals60
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize16MX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA60,8X15,32
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.002 A
Maximum slew rate0.33 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width8 mm
128Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
FEATURES
• PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
MT48LC32M4A2 – 8 Meg x 4 x 4 banks
MT48LC16M8A2 – 4 Meg x 8 x 4 banks
MT48LC8M16A2 – 2 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/dramds
PIN ASSIGNMENT (Top View)
54-Pin TSOP
x4 x8 x16
-
-
NC
DQ0
NC
DQ0
V
DD
DQ0
-
V
DD
Q
NC
DQ1
DQ1 DQ2
-
VssQ
NC
DQ3
DQ2 DQ4
-
V
DD
Q
NC
DQ5
DQ3 DQ6
-
VssQ
NC
DQ7
V
DD
-
NC DQML
-
WE#
-
CAS#
-
RAS#
CS#
-
BA0
-
BA1
-
A10
-
A0
-
A1
-
A2
-
A3
-
V
DD
-
x16 x8 x4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
-
-
NC
NC
-
NC
DQ1
-
OPTIONS
MARKING
NC
-
NC
• Configurations
32 Meg x 4 (8 Meg x 4 x 4 banks)
32M4
16 Meg x 8 (4 Meg x 8 x 4 banks)
16M8
8 Meg x 16 (2 Meg x 16 x 4 banks)
8M16
• WRITE Recovery (
t
WR)
t
WR = “2 CLK”
1
A2
• Package/Pinout
Plastic Package – OCPL
2
54-pin TSOP II (400 mil)
TG
54-pin TSOP II (400 mil) Lead-free
P
60-ball FBGA (8mm x 16mm)
FB
3
60-ball FBGA (8mm x 16mm)Lead-free BB
3
60-ball FBGA (11mm x 13mm)
FC
3
60-ball FBGA (11mm x 13mm) Lead-free BC
3
• Timing (Cycle Time)
10ns @ CL = 2 (PC100)
-8E
3,4,5
7.5ns @ CL = 3 (PC133)
-75
7.5ns @ CL = 2 (PC133)
-7E
6.0ns @ CL=3 (x16 only)
-6A
• Self Refresh
Standard
None
Low power
L
• Operating Temperature Range
Commercial (0
o
C to +70
o
C)
None
o
o
Industrial (-40 C to +85 C)
IT
3
NOTE:
1.
2.
3.
4.
5.
Refer to Micron Technical Note: TN-48-05.
Off-center parting line.
Consult Micron for availability.
Not recommended for new designs.
Shown for PC100 compatability.
-
-
-
-
-
-
-
-
-
-
-
-
-
Vss
DQ15 DQ7
VssQ
-
DQ14
NC
DQ13 DQ6
V
DD
Q
-
DQ12
NC
DQ11 DQ5
VssQ
-
DQ10
NC
DQ9 DQ4
V
DD
Q
-
DQ8
NC
-
Vss
-
NC
DQMH DQM
-
CLK
-
CKE
NC
-
A11
-
A9
-
A8
-
A7
-
A6
-
A5
-
A4
-
Vss
-
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
Note:
The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
32 Meg x 4
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
4K
4K (A0–A11)
4 (BA0, BA1)
2K (A0–A9, A11)
16 Meg x 8
4K
4K (A0–A11)
4 (BA0, BA1)
1K (A0–A9)
8 Meg x 16
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
KEY TIMING PARAMETERS
SPEED
GRADE
-6A
-7E
-7E
-75
-8E
3,4,5
-75
-8E
3 ,4,5
CLOCK
ACCESS TIME SETUP
FREQUENCY CL = 2* CL = 3* TIME
167 MHz
143 MHz
133 MHz
133 MHz
125 MHz
100 MHz
100 MHz
5.4ns
6ns
6ns
5.4ns
5.4ns
5.4ns
6ns
1.5ns
1.5ns
1.5ns
1.5ns
2ns
1.5ns
2ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
1ns
0.8ns
1ns
*CL = CAS (READ) latency
128Mb: x4, x8, x16 SDRAM
128MSDRAM_G.p65 – Rev. G; Pub. 10/03
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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