M28010
1 Mbit (128K x 8) Parallel EEPROM
With Software Data Protection
PRELIMINARY DATA
s
s
Fast Access Time: 100 ns
Single Supply Voltage:
– 4.5 V to 5.5 V for M28010
– 2.7 V to 3.6 V for M28010-W
– 1.8 V to 2.4 V for M28010-R
32
s
s
s
Low Power Consumption
Fast BYTE and PAGE WRITE (up to 128 Bytes)
Enhanced Write Detection and Monitoring:
– Data Polling
– Toggle Bit
– Page Load Timer Status
PDIP32 (BA)
1
s
s
s
s
s
s
JEDEC Approved Bytewide Pin-Out
Software Data Protection
Hardware Data Protection
Software Chip Erase
100000 Erase/Write Cycles (minimum)
Data Retention (minimum): 10 Years
PLCC32 (KA)
TSOP32 (NA)
8 x 20 mm
DESCRIPTION
The M28010 devices consist of 128Kx8 bits of low
power, parallel EEPROM, fabricated with
STMicroelectronics’ proprietary double polysilicon
CMOS technology. The devices offer fast access
time, with low power dissipation, and require a
single voltage supply (5V, 3V or 2V, depending on
the option chosen).
Table 1. Signal Names
A0-A16
DQ0-DQ7
W
E
G
V
CC
V
SS
Address Input
Data Input / Output
Write Enable
Figure 1. Logic Diagram
VCC
17
A0-A16
8
DQ0-DQ7
W
E
G
M28010
Chip Enable
Output Enable
Supply Voltage
Ground
VSS
AI02221
February 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/23
M28010
Figure 2A. DIP Connections
DU
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
M28010 25
24
23
22
21
20
19
18
17
AI02222
Figure 2C. TSOP Connections
VCC
W
DU
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
A14
DU
W
VCC
DU
A16
A15
A12
A7
A6
A5
A4
1
32
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
8
9
M28010
25
24
16
17
AI02224
Note: 1. DU = Do Not Use
Note: 1. DU = Do Not Use
Figure 2B. PLCC Connections
A12
A15
A16
DU
VCC
W
DU
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
G
A10
E
DQ7
9
M28010
25
data retention. The organization of the data in a 4
byte (32-bit) “word” format leads to significant
savings in power consumption. Once a byte has
been read, subsequent byte read cycles from the
same “word” (with addresses differing only in the
two least significant bits) are fetched from the
previously loaded Read Buffer, not from the
memory array. As a result, the power consumption
for these subsequent read cycles is much lower
than the power consumption for the first cycle. By
careful design of the memory access patterns, a
50% reduction in the power consumption is
possible.
SIGNAL DESCRIPTION
The external connections to the device are
summarized in Table 1, and their use in Table 3.
Addresses (A0-A16).
The address inputs are
used to select one byte from the memory array
during a read or write operation.
Data In/Out (DQ0-DQ7).
The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.
Chip Enable (E).
The chip enable input must be
held low to enable read and write operations.
When Chip Enable is high, power consumption is
reduced.
Output Enable (G).
The Output Enable input
controls the data output buffers, and is used to
initiate read operations.
17
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
AI02223
Note: 1. DU = Do Not Use
The device has been designed to offer a flexible
microcontroller interface, featuring both hardware
and software hand-shaking, with Data Polling and
Toggle Bit. The device supports a 128 byte Page
Write operation. Software Data Protection (SDP)
is also supported, using the standard JEDEC
algorithm.
The M28010 is designed for applications requiring
as much as 100,000 write cycles and ten years of
2/23
M28010
Table 2. Absolute Maximum Ratings
1
Symbol
T
A
T
STG
V
CC
V
IO
V
I
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature
Supply Voltage
Input or Output Voltage (except A9)
Input Voltage
Electrostatic Discharge Voltage (Human Body model)
2
Value
–40 to 85
–65 to 150
–0.3 to V
CCMAX
+1
–0.3 to V
CC
+0.6
–0.3 to 4.5
2000
Unit
°C
°C
V
V
V
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500
Ω)
Figure 3. Block Diagram
A7-A16
(Page Address)
ADDRESS
LATCH
X DECODE
1Mbit ARRAY
A0-A6
ADDRESS
LATCH
LATCH PAGE
Y DECODE
REFERENCES
VPP GEN
VREAD GEN
SENSE PAGE & DATA LATCH
E
G
W
CONTROL
LOGIC
PROGRAMMING
STATE
MACHINE
ECC
(1)
& MULTIPLEXER
I/O BUFFERS
DQ0-DQ7
AI02225
3/23
M28010
Table 3. Operating Modes
1
Mode
Read
Write
Stand-by / Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Note: 1. X = V
IH
or V
IL
.
E
V
IL
V
IL
V
IH
X
X
X
G
V
IL
V
IH
X
X
V
IL
V
IH
W
V
IH
V
IL
X
V
IH
X
X
DQ0-DQ7
Data Out
Data In
Hi-Z
Data Out or Hi-Z
Data Out or Hi-Z
Hi-Z
Write Enable (W).
The Write Enable input controls
whether the addressed location is to be read, from
or written to.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal V
CC
comparator
inhibits the Write operations if the V
CC
voltage is
lower than V
WI
(see Table 4A to Table 4C). Once
the voltage applied on the V
CC
pin goes over the
Table 4A. Power-Up Timing
1
for M28010 (5V range)
(T
A
= –40 to 85
°C;
V
CC
= 4.5 to 5.5 V)
Symbol
t
PUR
t
PUW
V
WI
Parameter
Time Delay to Read Operation
V
WI
threshold (V
CC
>V
WI
), write access to the
memory is allowed after a time-out t
PUW
, as
specified in Table 4A to Table 4C.
Further protection against data corruption is
offered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.
Min.
5
5
3.0
Max.
Unit
ms
ms
Time Delay to Write Operation (once V
CC
≥
V
WI
)
Write Inhibit Threshold
4.2
V
Note: 1. Sampled only, not 100% tested.
Table 4B. Power-Up Timing
1
for M28010-W (3V range)
(T
A
= –40 to 85
°C;
V
CC
= 2.7 to 3.6 V)
Symbol
t
PUR
t
PUW
V
WI
Parameter
Time Delay to Read Operation
Time Delay to Write Operation (once V
CC
≥
V
WI
)
Write Inhibit Threshold
Min.
5
5
2.0
2.6
Max.
Unit
ms
ms
V
Note: 1. Sampled only, not 100% tested.
Table 4C. Power-Up Timing
1
for M28010-R (2V range)
(T
A
= –40 to 85
°C;
V
CC
= 1.8 to 2.4 V)
Symbol
t
PUR
t
PUW
V
WI
Parameter
Time Delay to Read Operation
Time Delay to Write Operation (once V
CC
≥
V
WI
)
Write Inhibit Threshold
Min.
5
5
1.2
1.7
Max.
Unit
ms
ms
V
Note: 1. Sampled only, not 100% tested.
4/23
M28010
Read
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
Write
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as
shown in Figure 12 and Figure 13). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first).
After a delay, t
WLQ5H
, that cannot be shorter than
the value specified in Table 9A to Table 9C, the
internal write cycle starts. It continues, under
internal timing control, until the write operation is
complete. The commencement of this period can
be detected by reading the Page Load Timer
Status on DQ5. The end of the internal write cycle
Figure 4. Software Data Protection Enable Algorithms (with or without Memory Write)
SDP is Disabled and Application
needs to Enable it, and Write Data
SDP is Disabled and
Application needs to Enable it
Write AAh in
Address 5555h
Page Write
Timing
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Page Write
Timing
Write 55h in
Address 2AAAh
Write A0h in
Address 5555h
Write A0h in
Address 5555h
Write
is enabled
Time Out (tWLQ5H)
Write data
in any addresses
within one page
Wait for write completion (tQ5HQ5X)
SDP is set
Write AAh in
Address 5555h
Time Out (tWLQ5H)
Wait for write completion (tQ5HQ5X)
DATA has been written
and SDP is Enabled
Write 55h in
Address 2AAAh
Page Write
Timing
Write A0h in
Address 5555h
Write
is enabled
Write data
in any addresses
within one page
Time Out (tWLQ5H)
Wait for write completion (tQ5HQ5X)
DATA has been written
and SDP is Enabled
AI02227B
5/23
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