datasheet
EEWORLDEEWORLDEEWORLD
Datasheet
Part Number

Keyword

Search
Keyword

Part Number

Search
Datasheet> All Categories > storage> storage> IDT74ALVCH16701PA
PDF
Preview

IDT74ALVCH16701PA

Description
FIFO, 4X18, 5.5ns, Synchronous, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56
Categorystorage    storage   
File Size149KB，8 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT74ALVCH16701PA Overview

FIFO, 4X18, 5.5ns, Synchronous, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56

IDT74ALVCH16701PA Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instruction0.50 MM PITCH, TSSOP-56
Contacts56
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time5.5 ns
Other featuresCAN ALSO BE OPERATED AT 2.5V+/-0.2V
period time12 ns
JESD-30 codeR-PDSO-G56
JESD-609 codee0
length14 mm
memory density72 bit
memory width18
Humidity sensitivity level1
Number of functions1
Number of terminals56
word count4 words
character code4
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize4X18
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP56,.3,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/SerialPARALLEL
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
width6.1 mm

IDT74ALVCH16701PA Preview

IDT74ALVCH16701
3.3V CMOS 18-BIT READ/WRITE BUFFER WITH BUS-HOLD
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
READ/WRITE BUFFER
WITH BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
– V
CC
= 3.3V ± 0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– V
CC
= 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH16701:
– High Output Drivers: ±24mA
– Suitable for heavy loads
–
–
–
IDT74ALVCH16701
DESCRIPTION:
This 18-bit read/write buffer is built using advanced dual metal CMOS
technology. The ALVCH16701 is equipped with a four deep FIFO and
a read-back latch. It can be used as a read/write buffer between a CPU
and a memory or to interface a high-speed bus and a slow peripheral.
The A-to-B (write) path has a four deep FIFO for pipelined operations.
The FIFO can be reset and a FIFO full condition is indicated by the full
flag (FF). The B-to-A (read) path has a latch.
The ALVCH16701 has been designed with a ±24mA output driver.
This driver is capable of driving a moderate to heavy load while
maintaining speed performance.
The ALVCH16701 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistor.
APPLICATIONS:
•
3.3V High Speed Systems
•
3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
A
1:18
18
27
OEBA
RESET
CLK
W CE
RCE
FF
29
55
2
56
30
FIFO
(4 deep)
LATCH
28
LE
OEAB
1
18
B
1:18
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
SEPTEMBER 1999
DSC-4222/-
IDT74ALVCH16701
3.3V CMOS 18-BIT READ/WRITE BUFFER WITH BUS-HOLD
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
SO 56-1 44
SO 56-2
43
SO 56-3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
ABSOLUTE MAXIMUM RATING
Symbol
V
TERM(2)
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
OEAB
WCE
A
1
GN D
A
2
A
3
V
CC
A
4
A
5
A
6
GN D
A
7
A
8
A
9
A
10
A
11
A
12
GN D
A
13
A
14
A
15
V
CC
A
16
A
17
GN D
A
18
OEBA
LE
R CE
C LK
B
1
GN D
B
2
B
3
V
CC
B
4
B
5
B
6
GN D
B
7
B
8
B
9
B
10
B
11
B
12
GN D
B
13
B
14
B
15
V
CC
B
16
B
17
GN D
B
18
FF
R ESET
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NEW16link
NOTE:
1. As applicable to the device type.
SSOP/
TSSOP/TVSOP
TOP VIEW
c
2
IDT74ALVCH16701
3.3V CMOS 18-BIT READ/WRITE BUFFER WITH BUS-HOLD
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Names
A
1-18
B
1-18
CLK
I/O
I/O
I/O
I
18 bit I/O port
(1)
18 bit I/O port
(1)
Clock for write path FIFO. Clocks data into FIFO when WCE is low, clocks data out of FIFO when RCE is low. When FIFO is full all
further writes to the FIFO are inhibited. When FIFO is empty all reads from the FIFO are inhibited. CLK also resets the FIFO when
RESET is low.
Enable pin for FIFO input clock.
Enable pin for FIFO output clock.
Write path FIFO full flag. Goes low when FIFO is full.
Synchronous FIFO reset - when low CLK resets the FIFO. The FIFO pointers are initialized to the "empty" condition and FI FO output is
forced high (all ones). The FIFO full flag (FF) will be high immediately after reset.
Output enable pin for B port
Output enable pin for A port
Read path latch enable pin. When high, data flows transparently from B port to A port, B data is latched on the falling edge of LE.
Description
WCE
RCE
FF
RESET
OEAB
OEBA
LE
I
I
O
I
I
I
I
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs, outputs, or I/Os.
FUNCTION DESCRIPTION
This device is useful as a read/write buffer for modular high end
designs. It provides multi-level buffering in the write path and single
deep buffering in the read path, and is suited to write back cache
implementation. The read path provides a transparent latch.
The four deep FIFO uses one clock with two clock enable pins,
WCE and RCE to clock data in and out. The FIFO has an external full
flag which goes LOW when the FIFO is full. Internal read and write
pointers keep track of the words stored in the FIFO. A write attempt
to a full FIFO is ignored. An attempt read from an empty FIFO will
have no effect and the last read data remains at the output of the FIFO.
The FIFO may be reset by the synchronous RESET input. This resets
the read and write pointers to the original “empty” condition and also
sets all B outputs = 1. Simultaneous read and write attempts (clock
data into FIFO as well as clock data out of FIFO) are possible except
on FIFO empty and full boundaries. When the FIFO is empty, and a
simultaneous read and write is attempted, the read is ignored while
the write is executed. If the same is attempted when the FIFO is full,
the write is ignored while the read is executed. Normal operation of
the four deep FIFO in the write path is independent of the read path
operation.
FUNCTION TABLE
(1)
INPUTS
OEBA
H
L
L
H
H
L
OEAB
H
H
H
H
L
L
LE
H
H
L
X
X
L
RESET
H
H
H
H
H
H
CLK
↑
↑
↑
↑
↑
↑
Q
0
(B) Bus Hold
Ax
Q(B) Bus Hold
B to A
Q
0
(B)
Q
0
(A) Bus Hold
Q
0
(B) Bus Hold
A to B - 4 CLKS
Q
0
(B) - 4 CLKS Bus Hold
Case not recommended
OUTPUTS
Bx
Q
0
(A) -4CLKS Bus Hold
Transparent Mode
NOTES
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ =
LOW-to-HIGH Transition
3
IDT74ALVCH16701
3.3V CMOS 18-BIT READ/WRITE BUFFER WITH BUS-HOLD
EXTENDED COMMERCIAL TEMPERATURE RANGE
TIMING DIAGRAM
WRITE CYCLES
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 1
READ CYCLES
Cycle 2
Cycle 3
Cycle 4
CLK
RESET
WCE
OEAB
A [1:18]
FF
WORD 1
WORD 2
WORD 3
WORD 4
B [1:18]
RCE
WORD 1
WORD 2
WORD 3
WORD 4
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
40
µA
µA
V
mV
µA
µA
V
Unit
V
Quiescent Power Supply
Current Variation
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
4
IDT74ALVCH16701
3.3V CMOS 18-BIT READ/WRITE BUFFER WITH BUS-HOLD
EXTENDED COMMERCIAL TEMPERATURE RANGE
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
NEW16link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
Parameter
Power Dissipation Capacitance
Outputs enabled
Test Conditions
CLK Toggling
C
L
= 0pF, f = 10Mhz
C
PD
Power Dissipation Capacitance
Outputs enabled
One Bit Toggling
CLK Toggling
One Bit Toggling
Typical
28
26
10
9
V
CC
= 3.3V ± 0.3V
Typical
31
29
11
10
pF
Unit
pF
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
NEW16link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
5
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

Recommended Resources

Simple and practical remote control detector circuit diagram

Battery forklift circuit

Transformer tap regulator

Latched gas and smoke alarm circuits

Add AV2 interface and PAL60 function to remote control color TV

Oscillator circuit using frequency multiplier and M0S field effect transistor

Newbie seeking advice
I just learned dsp and finished the basics of interrupt EVA/B, but then I was confused and didn't know where to start. I would like to ask for your advice. Thank you....
liubuwei8888 DSP and ARM Processors
Digilent Shanghai recruits an engineer
[align=left][color=#333333][size=3]Digilent is recruiting an application engineer, working in Shanghai. [/size][/color][/align][align=left]Interested friends can [color=rgb(255, 0, 0)][size=4][b][url=...
eric_wang Recruitment
Experiment 9. Digital display experiment
The digital display using a single chip microcomputer should have a display device; the most widely used is the 7-segment digital tube. It is customary to say that it has 7 segments, but in fact it ha...
rain MCU
Good book sharing: "Example interpretation of 51 single-chip microcomputer complete learning and application"
Good book sharing, this is the best microcontroller learning book I have ever seen, everyone can take a look and know. http://product.dangdang.com/product.aspx?product_id=21066700ref=search-1-pub...
pheiedu MCU
Implementing Flash playback under WinCE
Has anyone implemented it before? How can I do it myself? The source code is so complicated that I don't know how to do it. I hope the seniors can guide me....
logics Embedded System
How does dsp filter the resonance of dc voltage? ? ? ?
How to use DSP to filter the resonance of DC voltage? ??? One method is to take multiple samples to get the average value, but this has a large resonance and the effect is not very good. Is there any ...
huangyiqian1000 DSP and ARM Processors
Shortcut:   S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components

  1. A-42225-0213
  2. WCR251210R4DELT
  3. 006224019004800
  4. SM42-18-27.0M-15F1CB
  5. VJ1812A561FNCAT
  6. 6102-20NT1RL1W
  7. RKC12DLSTP2004F
  8. SON-UN989-03-1602-A-B-1
  9. AME1117BCGT
  10. A2541WV-S-2x21P
  11. CR1210F1R10P05S
  12. SMRH5D18-220MT

Popular Articles

  1. LPC11U35 SSP/SPI learning notes
  2. Connective Peripherals series of connection products are available from element14
  3. Global growth in FWA equipment shipments due to Covid-19 lockdowns and shift to home working
  4. ZDS2022 Oscilloscope 100 Practical Videos 66: How to measure the frequency of abnormal glitches
  5. STM8 MCU reads DHT11 temperature and humidity sensor
  6. What are the characteristics and advantages of radar level meter
  7. Serial communication based on 51 single chip microcomputer (PC sends characters)
  8. 51 MCU Introduction - Basic Knowledge Summary
  9. MWC2022: Goodbye! The top Android smartphone maker is leaving, executives confirm
  10. How to use and pay attention to oscilloscope FFT spectrum analysis

Technical ResourceMore

  1. Design and simulation of octave electronic piano based on Multisim
  2. Chip Scale Components (CSM) and Their Applications in Miniature Power ICs
  3. National Electronic Design Competition
  4. ASP.NET Programming Basics and Applications Electronic Lesson Plan
  5. Design of Bluetooth temperature sensor
  6. Graduation Project Management Platform Based on SSH
  7. 8-bit single-chip microcontroller XC866
  8. Construction and application of satellite telemedicine information website
  9. Frequency calculation method analysis and error analysis
  10. Test Signal Analysis and Processing Technology of Virtual Instrument

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

About Us Customer Service Contact Information Datasheet Sitemap LatestNews
Index Files: 2424  2779  160  1677  2576  49  56  4  34  52 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号