HYMD264G726D(L)F8N-D43/J
DESCRIPTION
Hynix HYMD264G726D(L)F8N-D43/J series is registered 184-pin double data rate Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as 64Mx72 high-speed memory arrays.
Hynix HYMD264G726D(L)F8N-D43/J series consists of eighteen 32Mx8 DDR SDRAM in FBGA packages on a
184pin glass-epoxy substrate. Hynix HYMD264G726D(L)F8N-D43/J series provide a high performance 8-byte inter-
face in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD264G726D(L)F8N-D43/J series is designed for high speed of up to 166/200MHz and offers fully synchro-
nous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control
inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on
both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable
latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD264G726D(L)F8N-D43/J series incorporates SPD(serial presence detect). Serial presence detect func-
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
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512MB (64M x 72) Registered DDR DIMM based on
32Mx8 DDR SDRAM
JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
Error Check Correction (ECC) Capability
Registered inputs with one-clock delay
Phase-lock loop (PLL) clock driver to reduce loading
2.6V +/- 0.1V VDD and VDDQ Power supply for
DDR400, 2.5V +/- 0.2V VDD and VDDQ for
DDR333 supported
All inputs and outputs are compatible with SSTL_2
interface
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Fully differential clock operations (CK & /CK) with
166MHz/200MHz
Programmable CAS Latency 3 for DDR400,
2.5 for DDR333 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
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ORDERING INFORMATION
Part No.
HYMD264G726D(L)F8N-D43
HYMD264G726D(L)F8N-J
Power Supply
V
DD
=2.6V
V
DDQ
=2.6V
V
DD
=2.5V
V
DDQ
=2.5V
Clock Frequency
200MHz (*DDR400)
166MHz (*DDR333)
Interface
SSTL_2
SSTL_2
Form Factor
184pin Registered DIMM
5.25 x 1.125 x 0.15 inch
184pin Registered DIMM
5.25 x 1.125 x 0.15 inch
* JEDEC Defined Specifications compliant
Rev. 0.1 / Mar. 2004
2
HYMD264G726D(L)F8N-D43/J
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Voltage on V
DDQ
relative to V
SS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Þ Time
T
A
T
STG
V
IN
, V
OUT
V
DD
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
18
260 / 10
Rating
o
o
Unit
C
C
V
V
V
mA
W
o
C
/ Sec
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
Symbol
V
DD
V
DD
V
DDQ
V
DD
V
IH
V
IL
V
TT
V
REF
Min
2.3
2.5
2.3
2.5
V
REF
+ 0.15
-0.3
V
REF
- 0.04
0.49*VDDQ
Typ.
2.5
2.6
2.5
2.6
-
-
V
REF
0.5*VDDQ
Max
2.7
2.7
2.7
2.7
V
DDQ
+ 0.3
V
REF
- 0.15
V
REF
+ 0.04
0.51*VDDQ
Unit
V
V
V
V
V
V
V
V
3
2
4
1
1,4
Note
Note :
1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
4. For DDR400, VDD=2.6V +/- 0.1V, VDDQ=2.6V+/-0.1V
Rev. 0.1 / Mar. 2004
5
DSP and ARM Processors
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