GS8662D36BD-167I datasheet, PDF

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GS8662D36BD-167I: DescriptionStandard SRAM, 2MX36, 0.5ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, FPBGA-165; Categorystorage storage; File Size1MB，37 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8662D36BD-167I Overview

Standard SRAM, 2MX36, 0.5ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, FPBGA-165

GS8662D36BD-167I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	15 X 13 MM, 1 MM PITCH, FPBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.5 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	75497472 bit
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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Preliminary

GS8662D08/09/18/36BD-400/350/333/300/250

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 144 Mb devices

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb SigmaQuad-II

Burst of 4 SRAM

400 MHz–250 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

165-Bump, 13 mm x 15 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Because Separate I/O SigmaQuad-II B4 RAMs always transfer

data in four packets, A0 and A1 are internally set to 0 for the

first read or write transfer, and automatically incremented by 1

for the next transfers. Because the LSBs are tied off internally,

the address field of a SigmaQuad-II B4 RAM is always two

address pins less than the advertised index depth (e.g., the 4M

x 18 has a 1M addressable index).

SigmaQuad™ Family Overview

The GS8662D08/09/18/36BD are built in compliance with

the SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662D08/09/18/36BD SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8662D08/09/18/36BD SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

- 400

tKHKH

tKHQV

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

- 333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

Rev: 1.01 11/2010

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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