V437464S24VBTG-75 datasheet, PDF

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V437464S24VBTG-75: DescriptionSynchronous DRAM Module, 64MX72, 5.4ns, CMOS, DIMM-168; Categorystorage storage; File Size192KB，12 Pages; ManufacturerMosel Vitelic Corporation ( MVC ); Websitehttp://www.moselvitelic.com

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V437464S24VBTG-75 Overview

Synchronous DRAM Module, 64MX72, 5.4ns, CMOS, DIMM-168

V437464S24VBTG-75 Parametric

Parameter Name	Attribute value
Maker	Mosel Vitelic Corporation ( MVC )
Parts packaging code	DIMM
package instruction	DIMM, DIMM168
Contacts	168
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N168
memory density	4831838208 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	168
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM168
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum standby current	0.036 A
Maximum slew rate	4.32 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL

V437464S24VBTG-75 Preview

V437464S24V

3.3 VOLT 64M x 72 HIGH PERFORMANCE

UNBUFFERED ECC SDRAM MODULE

PRELIMINARY

168 Pin Unbuffered ECC 67,108,864 x 72 bit

Oganization SDRAM Modules

Utilizes High Performance 32M x 8 SDRAM in

TSOPII-54 Packages

Fully PC Board Layout Compatible to INTEL’S

Rev 1.0 Module Specification

Single +3.3V (± 0.3V) Power Supply

Programmable CAS Latency, Burst Length, and

Wrap Sequence (Sequential & Interleave)

Auto Refresh (CBR) and Self Refresh

All Inputs, Outputs are LVTTL Compatible

8192 Refresh Cycles every 64 ms

Serial Present Detect (SPD)

Speed

Grade

-75PC, CL=2,3

(133 MHz)

-75, CL=3

(133 MHz)

-10PC, CL=2,3

(100 MHz)

CILETIV LESOM

Features

Part Number

V437464S24VXTG-75PC

V437464S24VXTG-75

V437464S24VXTG-10PC

V437464S24V Rev. 1.0 January 2002

Description

The V437464S24V memory module is organized

67,108,864 x 72 bits in a 168 pin dual in line

memory module (DIMM). The 64M x 72 unbuffered

DIMM uses 18 Mosel-Vitelic 32M x 8 ECC SDRAM.

The x72 modules are ideal for use in high

performance computer systems where increased

memory density and fast access times are required.

Configuration

64M x 72

V437464S24V

Front

DQM1

CS0

VSS

A10(AP)

BA1

VCC

CLK0

VSS

CS2

DQM2

DQM3

VCC

CB2*

CB3*

VSS

I/O17

I/O18

Front

I/O19

I/O20

VCC

I/O21

CKE1

VSS

I/O22

I/O23

I/O24

VSS

I/O25

I/O26

I/O27

I/O28

VCC

I/O29

I/O30

I/O31

I/O32

VSS

CLK2

SDA

SCL

VCC

100

101

102

103

104

105

106

107

108

109

110

111

112

Back

VSS

I/O33

I/O34

I/O35

I/O36

VCC

I/O37

I/O38

I/O39

I/O40

I/O41

VSS

I/O42

I/O43

I/O44

I/O45

I/O46

VCC

I/O47

I/O48

CB4*

CB5*

VSS

VCC

CAS

DQM4

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

Back

DQM5

CS1

RAS

VSS

BA0

A11

VCC

CLK1

A12

VSS

CKE0

CS3

DQM6

DQM7

VCC

CB6*

CB7*

VSS

I/O49

I/O50

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

Back

I/O51

I/O52

VCC

I/O53

VSS

I/O54

I/O55

I/O56

VSS

I/O57

I/O58

I/O59

I/O60

VCC

I/O61

I/O62

I/O63

I/O64

VSS

CLK3

SA0

SA1

SA2

VCC

CILETIV LESOM

Front

VSS

I/O1

I/O2

I/O3

I/O4

VCC

I/O5

I/O6

I/O7

I/O8

I/O9

VSS

I/O10

I/O11

I/O12

I/O13

I/O14

VCC

I/O15

I/O16

CBO*

CB1*

VSS

VCC

DQM0

Pin Configurations (Front Side/Back Side)

Notes:

These pins are not used in this module.

Pin Names

A0–A12

I/O1–I/O64

RAS

CAS

BA0, BA1

CKE0, CKE1

CS0–CS3

CLK0–CLK3

DQM0–DQM7

VCC

VSS

SCL

Address Inputs

Data Inputs/Outputs

Row Address Strobe

Column Address Strobe

Read/Write Input

Bank Selects

Clock Enable

Chip Select

Clock Input

Data Mask

Power (+3.3 Volts)

Ground

Clock for Presence Detect

CB0–CB7

SA0–A2

SDA

Serial Data OUT for Presence

Detect

Serial Data IN for Presence

Detect

Check Bits (x72 Organization)

No Connection

Don’t Use

V437464S24V Rev. 1.0 January 2002

V437464S24V

Block Diagram

CS1

CS0

DQM0

I/O1–I/O8

10Ω

DQM1

I/O9–I/O16

10Ω

(BC7:0)

DQM CS

I/O1–I/O8 D16

DQM CS

I/O1–I/O8 D17

DQM5

I/O41–I/O48

DQM CS

I/O1–I/O8 D1

DQM CS

I/O1–I/O8 D9

DQM5

I/O41–I/O48

10Ω

DQM CS

I/O1–I/O8 D0

DQM CS

I/O1–I/O8 D8

DQM4

I/O33–I/O40

10Ω

DQM CS

I/O1–I/O8 D5

DQM CS

I/O1–I/O8 D13

DQM CS

I/O1–I/O8 D4

DQM CS

I/O1–I/O8 D12

CILETIV LESOM

MOSEL VITELIC

MANUFACTURED

Module Part Number Information

G - XX

SPEED

75PC = PC133 CL3,2

75 = PC133 CL3

10PC = PC133 CL3,2

LEAD FINISH

G = GOLD

SDRAM

3.3V

WIDTH

DEPTH

168 PIN Unbuffered

DIMM X8 COMPONENT

REFRESH

RATE 8K

COMPONENT

PACKAGE, T = TSOP

COMPONENT A=0.17u B=0.14u

REV LEVEL

LVTTL

4 BANKS

CS3

CS2

DQM2

I/O17–I/O24

10Ω

DQM3

I/O25–I/O32

10Ω

PROM SPD (256 WORD X 8 BIT)

SA0

SA1

SA2

SCL

SA0

SA1

SA2

SCL

SDA

47K

DQM

I/O1–I/O8 D2

DQM

I/O1–I/O8 D3

DQM

I/O1–I/O8 D10

DQM

I/O1–I/O8 D11

DQM6

I/O49–I/O56

10Ω

DQM7

I/O57–I/O64

10Ω

DQM

I/O1–I/O8 D6

DQM

I/O1–I/O8 D7

DQM

I/O1–I/O8 D14

DQM

I/O1–I/O8 D15

A11-A0, BA0, BA1

D0-D15 (D16, D17)

C0-C31, (C32...C35)

C33-C42

D0-D15 (D16, D17)

D0-D7 (D16)

10K

RAS, CAS, WE

CKE0

CLOCK WIRING

32M X 72

CLK0

CLK1

CLK2

CLK3

5 SDRAM

4 SDRAM +3.3pF

CKE1

D9-D15 (D17)

V437464S24V Rev. 1.0 January 2002

V437464S24V

written into the E

PROM device during module pro-

duction using a serial presence detect protocol (I

synchronous 2-wire bus)

A serial presence detect storage device –

PROM – is assembled onto the module. Informa-

tion about the module configuration, speed, etc. is

CILETIV LESOM

SPD-Table :

Memory Type

CS Latencies

WE Latencies

V437464S24V Rev. 1.0 January 2002

Serial Presence Detect Information

Byte Num-

ber

Function Described

Number of SPD bytes

Total bytes in Serial PD

Hex Value

SPD Entry Value

128

256

SDRAM

-75PC

-75

-10PC

Number of Row Addresses (without BS bits)

Number of Column Addresses (for x8

SDRAM)

Number of DIMM Banks

Module Data Width

Module Data Width (continued)

Module Interface Levels

SDRAM Cycle Time at CL=3

SDRAM Access Time from Clock at CL=3

Dimm Config (Error Det/Corr.)

Refresh Rate/Type

SDRAM width, Primary

Error Checking SDRAM Data Width

Minimum Clock Delay from Back to Back

Random Column Address

Burst Length Supported

Number of SDRAM Banks

Supported CAS Latencies

LVTTL

7.5 ns/10.0 ns

5.4 ns/6.0 ns

ECC

Self-Refresh, 7.8µs

n/a / x8

ccd

= 1 CLK

1, 2, 4, 8

CL = 3, 2

CS Latency = 0

WL = 0

Non Buffered/Non Reg.

Vcc tol ± 10%

7.5 ns/10.0 ns

SDRAM DIMM Module Attributes

SDRAM Device Attributes: General

Minimum Clock Cycle Time at CAS Latency

Maximum Data Access Time from Clock for

CL = 2

Minimum Clock Cycle Time at CL = 1

Maximum Data Access Time from Clock at

CL = 1

Minimum Row Precharge Time

5.4 ns/6.0 ns

Not Supported

15 ns /20 ns

V437464S24V

CILETIV LESOM

62-61

65-71

73-90

91-92

95-98

99-125

126

127

128+

SPD Revision

Reserved

SPD-Table : (Continued)

Byte Num-

ber

Function Described

Minimum Row Active to Row Active Delay

RRD

Minimum RAS to CAS Delay t

RCD

Minimum RAS Pulse Width t

RAS

Module Bank Density (Per Bank)

SDRAM Input Setup Time

SDRAM Input Hold Time

SDRAM Data Input Setup Time

SDRAM Data Input Hold Time

Superset Information (May be used in Fu-

ture)

Revision 2/1.2

Hex Value

SPD Entry Value

14 ns/15 ns/16 ns

-75PC

-75

-10PC

15 ns/20 ns

42 ns/45 ns

256 MByte

1.5 ns/2.0 ns

0.8 ns/1.0 ns

1.5 ns/2.0 ns

0.8 ns/1.0 ns

Checksum for Bytes 0 - 62

Manufacturer’s JEDEC ID Code

Manufacturer’s JEDEC ID Code (cont.)

Manufacturing Location

Module Part Number (ASCII)

PCB Identification Code

Assembly Manufacturing Date (Year)

Assembly Manufacturing Date (Week)

Assembly Serial Number

V437464S24V

Mosel Vitelic

Intel Specification for Frequency

Unused Storage Location

DC Characteristics

= 0°C to 70°C; V

= 0 V; V

, V

DDQ

= 3.3V

0.3V

Limit Values

Symbol

Parameter

Input High Voltage

Input Low Voltage

Output High Voltage (I

OUT

= –4.0 mA)

Min.

2.0

–0.5

2.4

Max.

+0.3

0.8

—

Unit

V437464S24V Rev. 1.0 January 2002

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Description	Synchronous DRAM Module, 64MX72, 5.4ns, CMOS, DIMM-168	Synchronous DRAM Module, 64MX72, 5.4ns, CMOS, DIMM-168	Synchronous DRAM Module, 64MX72, 5.4ns, CMOS, DIMM-168	Synchronous DRAM Module, 64MX72, 5.4ns, CMOS, DIMM-168	Synchronous DRAM Module, 64MX72, 6ns, CMOS, DIMM-168	Synchronous DRAM Module, 64MX72, 6ns, CMOS, DIMM-168
Maker	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )
Parts packaging code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
package instruction	DIMM, DIMM168	DIMM, DIMM168	DIMM, DIMM168	DIMM, DIMM168	DIMM, DIMM168	DIMM, DIMM168
Contacts	168	168	168	168	168	168
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	5.4 ns	5.4 ns	5.4 ns	5.4 ns	6 ns	6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz	133 MHz	133 MHz	133 MHz	100 MHz	100 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-XDMA-N168	R-XDMA-N168	R-XDMA-N168	R-XDMA-N168	R-XDMA-N168	R-XDMA-N168
memory density	4831838208 bit	4831838208 bit	4831838208 bit	4831838208 bit	4831838208 bit	4831838208 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE
memory width	72	72	72	72	72	72
Number of functions	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1
Number of terminals	168	168	168	168	168	168
word count	67108864 words	67108864 words	67108864 words	67108864 words	67108864 words	67108864 words
character code	64000000	64000000	64000000	64000000	64000000	64000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	64MX72	64MX72	64MX72	64MX72	64MX72	64MX72
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
Encapsulate equivalent code	DIMM168	DIMM168	DIMM168	DIMM168	DIMM168	DIMM168
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192	8192
self refresh	YES	YES	YES	YES	YES	YES
Maximum standby current	0.036 A	0.036 A	0.036 A	0.036 A	0.036 A	0.036 A
Maximum slew rate	4.32 mA	4.32 mA	4.32 mA	4.32 mA	3.96 mA	3.96 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL

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