SC16C752
Dual UART with 64-byte FIFO
Rev. 04 — 20 June 2003
Product data
1. Description
The SC16C752 is a dual universal asynchronous receiver/transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to
5 Mbits/s (3.3 V and 5 V). The SC16C752 offers enhanced features. It has a
transmission control register (TCR) that stores receiver FIFO threshold levels to
start/stop transmission during hardware and software flow control. With the FIFO
RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one
access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be
programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can
transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect
break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can
detect FIFO underflow. The UART also contains a software interface for modem
control operations, and has software flow control and hardware flow control
capabilities.
The SC16C752 is available in a plastic LQFP48 package.
2. Features
s
Pin compatible with SC16C2550 with additional enhancements
s
Up to 5 Mbits/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is
3 Mbits/s)
s
64-byte transmit FIFO
s
64-byte receive FIFO with error flags
s
Programmable and selectable transmit and receive FIFO trigger levels for DMA
and interrupt generation
s
Software/hardware flow control
x
Programmable Xon/Xoff characters
x
Programmable auto-RTS and auto-CTS
s
Optional data flow resume by Xon any character
s
DMA signalling capability for both received and transmitted data
s
Supports 5 V, 3.3 V and 2.5 V operation
s
Software selectable baud rate generator
s
Prescaler provides additional divide-by-4 function
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
s
Fast databus access time
s
Programmable sleep mode
s
Programmable serial interface characteristics
x
5, 6, 7, or 8-bit characters
x
Even, odd, or no parity bit generation and detection
x
1, 1.5, or 2 stop bit generation
s
False start bit detection
s
Complete status reporting capabilities in both normal and sleep mode
s
Line break generation and detection
s
Internal test and loop-back capabilities
s
Fully prioritized interrupt system controls
s
Modem control functions (CTS, RTS, DSR, DTR, RI, and CD).
3. Ordering information
Table 1:
Ordering information
Package
Name
SC16C752IB48
LQFP48
Description
plastic low profile quad flat package; 48 leads; body 7
×
7
×
1.4 mm
Version
SOT313-2
Type number
9397 750 11635
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
2 of 47
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
4. Block diagram
SC16C752
TRANSMIT
FIFO
REGISTER
D0–D7
IOR
IOW
RESET
DATA BUS
AND
CONTROL LOGIC
TRANSMIT
SHIFT
REGISTER
TXA, TXB
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RXA, RXB
A0–A2
CSA
CSB
REGISTER
SELECT
LOGIC
DTRA, DTRB
RTSA, RTSB
OPA, OPB
MODEM
CONTROL
LOGIC
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
002aaa225
XTAL1
XTAL2
Fig 1. Block diagram.
9397 750 11635
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
3 of 47
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
5. Pinning information
5.1 Pinning
43 TXRDYA
39 DSRA
38 CTSA
42 VCC
40 CDA
41 RIA
D5
D6
D7
RXB
RXA
TXRDYB
TXA
TXB
OPB
1
2
3
4
5
6
37 NC
48 D4
47 D3
46 D2
45 D1
44 D0
36 RESET
35 DTRB
34 DTRA
33 RTSA
32 OPA
31 RXRDYA
SC16C752IB48
7
8
9
30 INTA
29 INTB
28 A0
27 A1
26 A2
25 NC
CSA 10
CSB 11
NC 12
XTAL1 13
XTAL2 14
IOW 15
CDB 16
GND 17
RXRDYB 18
IOR 19
DSRB 20
RIB 21
RTSB 22
CTSB 23
NC 24
002aaa224
Fig 2. Pin configuration.
5.2 Pin description
Table 2:
Symbol
A0
A1
A2
CDA, CDB
Pin description
Pin
28
27
26
40, 16
Type
I
I
I
I
Description
Address 0 select bit.
Internal registers address selection.
Address 1 select bit.
Internal registers address selection.
Address 2 select bit.
Internal registers address selection.
Carrier Detect (Active-LOW).
These inputs are associated with individual UART
channels A and B. A logic LOW on these pins indicates that a carrier has been
detected by the modem for that channel. The state of these inputs is reflected in the
modem status register (MSR).
Chip Select (Active-LOW).
These pins enable data transfers between the user CPU
and the SC16C752 for the channel(s) addressed. Individual UART sections (A, B) are
addressed by providing a logic LOW on the respective CSA and CSB pins.
CSA, CSB
10, 11
I
9397 750 11635
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
4 of 47
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Table 2:
Symbol
Pin description
…continued
Pin
38, 23
Type
I
Description
Clear to Send (Active-LOW).
These inputs are associated with individual UART
channels A and B. A logic 0 (LOW) on the CTS pins indicates the modem or data set is
ready to accept transmit data from the SC16C752. Status can be tested by reading
MSR[4]. These pins only affect the transmit and receive operations when Auto-CTS
function is enabled via the Enhanced Feature Register EFR[7] for hardware flow
control operation.
Data bus (bi-directional).
These pins are the 8-bit, 3-state data bus for transferring
information to or from the controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
Data Set Ready (Active-LOW).
These inputs are associated with individual UART
channels A and B. A logic 0 (LOW) on these pins indicates the modem or data set is
powered-on and is ready for data exchange with the UART. The state of these inputs is
reflected in the modem status register (MSR).
Data Terminal Ready (Active-LOW).
These outputs are associated with individual
UART channels A and B. A logic 0 (LOW) on these pins indicates that the SC16C752
is powered-on and ready. These pins can be controlled via the modem control register.
Writing a logic 1 to MCR[0] will set the DTR output to logic 0 (LOW), enabling the
modem. The output of these pins will be a logic 1 after writing a logic 0 to MCR[0], or
after a reset.
Signal and power ground.
Interrupt A and B (Active-HIGH).
These pins provide individual channel interrupts
INTA and INTB. INTA and INTB are enabled when MCR[3] is set to a logic 1, interrupt
sources are enabled in the interrupt enable register (IER). Interrupt conditions include:
receiver errors, available receiver buffer data, available transmit buffer space, or when
a modem status flag is detected. INTA, INTB are in the high-impedance state after
reset.
Input/Output Read strobe (Active-LOW).
A HIGH-to-LOW transition on IOR will load
the contents of an internal register defined by address bits A0-A2 onto the SC16C752
data bus (D0-D7) for access by external CPU.
Input/Output Write strobe (Active-LOW).
A LOW-to-HIGH transition on IOW will
transfer the contents of the data bus (D0-D7) from the external CPU to an internal
register that is defined by address bits A0-A2 and CSA and CSB.
Not connected.
User defined outputs.
This function is associated with individual channels A and B.
The state of these pins is defined by the user through the software settings of MCR[3].
INTA-INTB are set to active mode and OPA-OPB to a logic 0 when MCR[3] is set to a
logic 1. INTA-INTB are set to the 3-State mode and OPA-OPB to a logic 1 when
MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset.
Reset.
This pin will reset the internal registers and all the outputs. The UART
transmitter output and the receiver input will be disabled during reset time. RESET is
an active-HIGH input.
Ring Indicator (Active-LOW).
These inputs are associated with individual UART
channels, A and B. A logic 0 on these pins indicates the modem has received a ringing
signal from the telephone line. A LOW-to-HIGH transition on these input pins
generates a modem status interrupt, if enabled. The state of these inputs is reflected
in the modem status register (MSR).
CTSA, CTSB
D0-D4,
D5-D7
DSRA, DSRB
44-48,
1-3
39, 20
I/O
I
DTRA, DTRB
34, 35
O
GND
INTA, INTB
17
30, 29
I
O
IOR
19
I
IOW
15
I
NC
OPA, OPB
12, 24,
25, 37
32, 9
-
O
RESET
36
I
RIA, RIB
41, 21
I
9397 750 11635
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
5 of 47
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