K8F1215EBM-SE1F0 datasheet, PDF

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K8F1215EBM-SE1F0: DescriptionFlash, 32MX16, 110ns, PBGA64, 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64; Categorystorage storage; File Size1MB，72 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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K8F1215EBM-SE1F0 Overview

Flash, 32MX16, 110ns, PBGA64, 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64

K8F1215EBM-SE1F0 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64
Contacts	64
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Maximum access time	110 ns
Other features	SYNCHRONOUS BURST MODE OPERATION IS ALSO POSSIBLE
startup block	BOTTOM
JESD-30 code	R-PBGA-B64
JESD-609 code	e1
length	11 mm
memory density	536870912 bit
Memory IC Type	FLASH
memory width	16
Humidity sensitivity level	2
Number of functions	1
Number of terminals	64
word count	33554432 words
character code	32000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	32MX16
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Programming voltage	1.8 V
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
type	NOR TYPE
width	9 mm

K8F1215EBM-SE1F0 Preview

Advanced Information

K8F12(13)15ET(B)M

Flash Memory

512Mb M-die MLC NOR Specification

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

-1-

Revision 0.0

November 2007

Advanced Information

K8F12(13)15ET(B)M

Flash Memory

Document Title

512M Bit (32M x16) Muxed Burst , Multi Bank MLC NOR Flash Memory

Revision History

Revision No.

0.0

- Initial

Revision

- Correct Icc2(Active Write Current) from 15mA(min), 30mA(max)

to 25mA(typ), 40mA(max)

- Correct default value of programmable wait state from A11~A14

"1010"(Data valid on the 14th active CLK) to "1011"(Data valid on the

15th active CLK)

- Correct the description of Figure 4(Continuous Burst Mode

Read@133MHz) for exact explanation of initial access time.

- Correct the description of Figure 5(Continuous Burst Mode

Read@108MHz) for exact explanation of initial access time.

- Correct the description of Figure 6(8 word Linear Burst Mode with

Wrap Around@133MHz) for exact explanation of initial access time.

- Correct the description of Figure 7(8 word Linear Burst with RDY Set

One Cycle Before Data) for exact explanation of initial access time.

- Correct tBA(Burst Access Time Valid Clock to Output Delay)

from 8ns(@83Mhz) to 9ns(@83MHz)

- Correct tBDH(Data Hold Time from Next Clock Cycle) from

4ns(@66MHz), 2.25ns(@108MHz), 1.5ns(@133MHz) to

3ns(@66MHz), 2ns(@108MHz), 2ns(@133MHz)

- Correct tRDYA(Clock to RDY Setup Time) from 8ns(@83Mhz) to

9ns(@83MHz)

- Correct tRDYS(RDY setup to Clock) from 4ns(@66MHz),

2.25ns(@108MHz), 1.5ns(@133MHz) to 3ns(@66MHz),

2ns(@108MHz), 2ns(@133MHz)

- Correct typo

- Modify figures for first word boundary crossing

- Modify output driver setting table

- Change tAVDH(AVD Hold Time from CLK) from 6ns(@66MHz),

5ns(@83MHz) to 2ns(@66/83MHz)

- Changes tAAVDH(Address Hold Time from Rising Egde of AVD)

from 7ns(@66MHz), 5ns(@83MHz) to 2ns(@66/83MHz)

- Change tCES(CE Setup Time to CLK) from 4.5ns @133MHz to 6ns

@133MHz

- Add Ordering Information for Density

12 : 512Mb for 66/83MHz, 13 : 512Mb for 108/133Mhz

- Add Product Classification Table (Table 1-1)

- CFI note is added (Max Operation frequency : Data 53H is in 66/

83Mhz part

- Correct typo

- Specification is finalized

Active Asynchronous read Current(@1Mhz) is changed

3mA(typ.),5mA(max.) to 8mA(typ.), 10mA(max.)

'In erase/program suspend followed by resume operation, min. 200ns is

needed for checking the busy status' is added

- Frequency information is added to Programmable Wait State at Burst

Mode Configuration Register Table.

- "Asynchronous mode may not support read following four sequential

invalid read condition within 200ns." is added

History

Draft Date

October 20, 2005

Remark

Advanced

0.1

October 28, 2005

Advanced

0.2

December 20, 2005

Advanced

0.3

April 04, 2006

Advanced

1.0

June 08, 2006

1.1

September 08, 2006

-2-

Revision 0.0

November 2007

Advanced Information

K8F12(13)15ET(B)M

1.2

1.3

- Correct typo

- Package Dimension is updated

- Correct typo

- DPD description is added

- Multi-block erase operation description is added in Fig. 13

- Block protection/unprotection

BA514 and BA513 in Top boot device, BA0 and BA1 in Bottom boot

device is added

- tAVDO timing is added.

- CLK characterization is added.

- tBA, tBDH description is added.

- Async. read parameter table is changed.

- Table number is changed.

- tAH is changed 7ns to 2ns

Flash Memory

September 28, 2006

April 09, 2007

1.4

July 25, 2007

1.5

1.6

August 06, 2007

August 20, 2007

-3-

Revision 0.0

November 2007

K8F12(13)15ET(B)M

512Mb M-die MLC NOR Specification 1

Flash Memory

1. 0 FEATURES................................................................................................................................................................ 4

1.1. GENERAL DESCRIPTION ........................................................................................................................................ 4

1.2. PIN DESCRIPTION ................................................................................................................................................... 5

1.3. 64 Ball FBGA TOP VIEW (BALL DOWN).................................................................................................................. 5

1.4. FUNCTIONAL BLOCK DIAGRAM............................................................................................................................. 6

2. 0 ORDERING INFORMATION ..................................................................................................................................... 7

3. 0 PRODUCT INTRODUCTION .................................................................................................................................... 9

4. 0 COMMAND DEFINITIONS ........................................................................................................................................ 10

5. 0 DEVICE OPERATION ............................................................................................................................................... 12

5.1. Read Mode ............................................................................................................................................................... 12

5.1.1 Asynchronous Read Mode ................................................................................................................................... 12

5.1.2 Synchronous (Burst) Read Mode .......................................................................................................................... 12

5.1.3 Continuous Linear Burst Read .............................................................................................................................. 12

5.1.4 Programmable Wait State ..................................................................................................................................... 13

5.1.5 Handshaking ......................................................................................................................................................... 13

5.2. Set Burst Mode Configuration Register ..................................................................................................................... 14

5.2.1 Programmable Wait State Configuration............................................................................................................... 14

5.2.2 Burst Read Mode Setting ...................................................................................................................................... 14

5.2.3 RDY Configuration ................................................................................................................................................ 15

5.3. Output Driver Setting ................................................................................................................................................. 15

5.4. Autoselect Mode ........................................................................................................................................................ 16

6. 0 Standby Mode............................................................................................................................................................ 16

6.1. Automatic Sleep Mode............................................................................................................................................... 16

6.2. Output Disable Mode ................................................................................................................................................. 16

7. 0 Block Protection & Unprotection ................................................................................................................................ 16

8. 0 Hardware Reset......................................................................................................................................................... 17

8.1. Software Reset .......................................................................................................................................................... 17

9. 0 Program ..................................................................................................................................................................... 17

9.1. Accelerated Program ................................................................................................................................................. 17

9.2. Writer Buffer Programming ........................................................................................................................................ 18

9.3. Accelerated Write Buffer Programming ..................................................................................................................... 18

10. 0 Chip Erase ............................................................................................................................................................... 19

10.1. Block Erase.............................................................................................................................................................. 19

11. 0 Unlock Bypass ......................................................................................................................................................... 19

12. 0 Erase Suspend / Resume........................................................................................................................................ 19

12.1. Program Suspend / Resume ................................................................................................................................... 20

13. 0 Read While Write Operation .................................................................................................................................... 20

14. 0 OTP Block Region ................................................................................................................................................... 20

14.1. Customer Lockable.................................................................................................................................................. 20

15. 0 Low VCC Write Inhibit.............................................................................................................................................. 20

15.1. Write Pulse “Glitch” Protection................................................................................................................................. 20

15.2. Logical Inhibit........................................................................................................................................................... 20

16. 0 FLASH MEMORY STATUS FLAGS ........................................................................................................................ 21

16.1. DQ7 : Data Polling ................................................................................................................................................... 21

16.2. DQ6 : Toggle Bit ...................................................................................................................................................... 21

16.3. DQ5 : Exceed Timing Limits .................................................................................................................................... 21

16.4. DQ3 : Block Erase Timer ......................................................................................................................................... 22

16.5. DQ2 : Toggle Bit 2 ................................................................................................................................................... 22

16.6. DQ1 : Buffer Program Abort Indicator...................................................................................................................... 22

16.7. RDY: Ready............................................................................................................................................................. 22

-1-

Revision 1.6

August 2007

K8F12(13)15ET(B)M

Flash Memory

17. 0 Deep Power Down................................................................................................................................................... 23

18. 0 Commom Flash Memory Interface .......................................................................................................................... 24

19. 0 Crossing of First Word Boundary in Burst Read Mode............................................................................................ 41

-2-

Revision 1.6

August 2007

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K8F1215EBM-SE1F0 Related Products

	K8F1215EBM-SE1F0	K8F1215ETM-SC1F0	K8F1215ETM-SE1F0	K8F1215ETM-FC1F0	K8F1215EBM-SC1F0	K8F1215EBM-FC1F0	K8F1215EBM-FE1F0	K8F1215ETM-FE1F0
Description	Flash, 32MX16, 110ns, PBGA64, 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64	Flash, 32MX16, 110ns, PBGA64, 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64	Flash, 32MX16, 110ns, PBGA64, 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64	Flash, 32MX16, 110ns, PBGA64, 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, FBGA-64	Flash, 32MX16, 110ns, PBGA64, 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64	Flash, 32MX16, 110ns, PBGA64, 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, FBGA-64	Flash, 32MX16, 110ns, PBGA64, 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, FBGA-64	Flash, 32MX16, 110ns, PBGA64, 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, FBGA-64
Is it Rohs certified?	conform to	conform to	conform to	incompatible	conform to	incompatible	incompatible	incompatible
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64	9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64	9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64	9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, FBGA-64	9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64	9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, FBGA-64	9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, FBGA-64	9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, FBGA-64
Contacts	64	64	64	64	64	64	64	64
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compli
ECCN code	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A
Maximum access time	110 ns	110 ns	110 ns	110 ns	110 ns	110 ns	110 ns	110 ns
Other features	SYNCHRONOUS BURST MODE OPERATION IS ALSO POSSIBLE	SYNCHRONOUS BURST MODE OPERATION IS ALSO POSSIBLE	SYNCHRONOUS BURST MODE OPERATION IS ALSO POSSIBLE	SYNCHRONOUS BURST MODE OPERATION IS ALSO POSSIBLE	SYNCHRONOUS BURST MODE OPERATION IS ALSO POSSIBLE	SYNCHRONOUS BURST MODE OPERATION IS ALSO POSSIBLE	SYNCHRONOUS BURST MODE OPERATION IS ALSO POSSIBLE	SYNCHRONOUS BURST MODE OPERATION IS ALSO POSSIBLE
startup block	BOTTOM	TOP	TOP	TOP	BOTTOM	BOTTOM	BOTTOM	TOP
JESD-30 code	R-PBGA-B64	R-PBGA-B64	R-PBGA-B64	R-PBGA-B64	R-PBGA-B64	R-PBGA-B64	R-PBGA-B64	R-PBGA-B64
JESD-609 code	e1	e1	e1	e0	e1	e0	e0	e0
length	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm
memory density	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bi
Memory IC Type	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH
memory width	16	16	16	16	16	16	16	16
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	64	64	64	64	64	64	64	64
word count	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words
character code	32000000	32000000	32000000	32000000	32000000	32000000	32000000	32000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	70 °C	85 °C	70 °C	70 °C	70 °C	85 °C	85 °C
organize	32MX16	32MX16	32MX16	32MX16	32MX16	32MX16	32MX16	32MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VFBGA	VFBGA	VFBGA	VFBGA	VFBGA	VFBGA	VFBGA	VFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	NOT SPECIFIED	260	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Programming voltage	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Maximum supply voltage (Vsup)	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	COMMERCIAL	OTHER	COMMERCIAL	COMMERCIAL	COMMERCIAL	OTHER	OTHER
Terminal surface	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN LEAD	TIN SILVER COPPER	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	40	40	40	NOT SPECIFIED	40	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
type	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE
width	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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