K9K1216D0C-JCB00 datasheet, PDF

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K9K1216D0C-JCB00: DescriptionFlash, 32MX16, 30ns, PBGA63, 9 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, FBGA-63; Categorystorage storage; File Size955KB，39 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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K9K1216D0C-JCB00 Overview

Flash, 32MX16, 30ns, PBGA63, 9 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, FBGA-63

K9K1216D0C-JCB00 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	TFBGA, BGA63,10X12,32
Contacts	63
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Maximum access time	30 ns
command user interface	YES
Data polling	NO
JESD-30 code	R-PBGA-B63
length	11 mm
memory density	536870912 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	4K
Number of terminals	63
word count	33554432 words
character code	32000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA63,10X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
page size	256 words
Parallel/Serial	PARALLEL
power supply	2.65 V
Programming voltage	2.7 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	8K
Maximum standby current	0.00005 A
Maximum slew rate	0.02 mA
Maximum supply voltage (Vsup)	2.9 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.65 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
switch bit	NO
width	9 mm

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K9K1208Q0C

K9K1208D0C

K9K1208U0C

K9K1216Q0C

K9K1216D0C

K9K1216U0C

FLASH MEMORY

Document Title

64M x 8 Bit , 32M x 16 Bit NAND Flash Memory

Revision History

Revision No. History

0.0

1.0

Initial issue.

1.Pin assignment of TBGA dummy ball is changed.

(before) DNU --> (after) N.C

2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 34)

3. Add the data protection Vcc guidence for 1.8V device - below about

1.1V. (Page 35)

4. Add the specification of Block Lock scheme.(Page 29~32)

5. Pin assignment of TBGA A3 ball is changed.

(before) N.C --> (after) Vss

2.0

1. The Maximum operating current is changed.

Read : Icc1 20mA-->30mA

Program : Icc2 20mA-->40mA

Erase : Icc3 20mA-->40mA

The min. Vcc value 1.8V devices is changed.

K9K12XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V

Pb-free Package is added.

K9K1208U0C-HCB0,HIB0

K9K12XXQ0C-HCB0,HIB0

K9K1216U0C-HCB0,HIB0

K9K1216Q0C-HCB0,HIB0

Errata is added.(Front Page)-K9K12XXQ0C

tWC tWP tRC tREH tRP tREA tCEA

Specification

45 25 50 15 25 30

Relaxed value 60 40 60 20 40 40

1. Max. Thickness of TBGA packge is changed.

0.09

±0.10

(Before)

-->

1.10

±0.10

(After)

2. New definition of the number of invalid blocks is added.

(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb

memory space.)

1. The guidence of LOCKPRE pin usage is changed.

Don’t leave it N.C. Not using LOCK MECHANISM & POWER-ON AUTO-

READ, connect it Vss.(Before)

--> Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect

it Vss or leave it N.C(After)

2. 2.65V device is added.

3. Note is added.

(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for

durations of 20 ns or less.)

Jan. 17th 2003

Preliminary

Draft Date

Sep. 12th 2002

Jan. 3rd 2003

Remark

Advance

2.1

Mar. 5th 2003

Preliminary

2.2

Mar. 13rd 2003

2.3

Mar. 17th 2003

2.4

Apr. 4th 2003

2.5

Jul. 4th 2003

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.

http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

K9K1208Q0C

K9K1208D0C

K9K1208U0C

K9K1216Q0C

K9K1216D0C

K9K1216U0C

FLASH MEMORY

PIN DESCRIPTION

Pin Name

I/O

~ I/O

(K9K1208X0C)

I/O

~ I/O

(K9K1216X0C)

Pin Function

DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The I/

O pins float to high-z when the chip is deselected or when the outputs are disabled.

I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-

ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and

output.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and

the device does not return to standby mode in program or erase operation. Regarding CE control during

read operation, refer to ’Page read’ section of Device operation .

READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE pulse.

WRITE PROTECT

The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage

generator is reset when the WP pin is active low. When LOCKPRE is a logic high and WP is a logic low, the

all blocks go to lock state.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or

random read operation is in process and returns to high state upon completion. It is an open drain output and

does not float to high-z condition when the chip is deselected or when outputs are disabled.

OUTPUT BUFFER POWER

Vcc

is the power supply for Output Buffer.

Vcc

is internally connected to Vcc, thus should be biased to Vcc.

POWER

is the power supply for device.

GROUND

NO CONNECTION

Lead is not internally connected.

DO NOT USE

Leave it disconnected

LOCK MECHANISM & POWER-ON AUTO-READ ENABLE

To Enable and disable the Lock mechanism and Power On Auto Read. When LOCKPRE is a logic high,

Block Lock mode and Power-On Auto-Read mode are enabled, and when LOCKPRE is a logic low, Block

Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only on

3.3V device(K9K12XXU0C)

Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it N.C

CLE

ALE

R/B

Vcc

Vss

N.C

DNU

LOCKPRE

NOTE

: Connect all V

and V

pins of each device to common power supply outputs.

Do not leave V

or V

disconnected.

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