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3.3 V Upstream
Cable Line Driver
AD8324
FEATURES
Supports DOCSIS 2.0 and Euro-DOCSIS standards for
reverse path transmission systems
Gain programmable in 1 dB steps over a 59 dB range
Low distortion at 61 dBmV output:
–59 dBc SFDR at 21 MHz
–54 dBc SFDR at 65 MHz
Output noise level @ minimum gain 1.3 nV/√Hz
Maintains 75 Ω output impedance in TX-enable and
Transmit-disable condition
Upper bandwidth: 100 MHz (full gain range)
3.3 V supply operation
Supports SPI® interfaces
FUNCTIONAL BLOCK DIAGRAM
BYP
V
IN+
DIFF
OR SINGLE
INPUT
AMP
VERNIER
ATTENUATION
CORE
OUTPUT
STAGE
V
OUT+
V
IN–
V
OUT–
8
DECODE
8
POWER-
DOWN LOGIC
RAMP
Z
OUT
DIFF =
75Ω
Z
IN
(SINGLE) = 550Ω
Z
IN
(DIFF) = 1100Ω
AD8324
DATA LATCH
8
04339-0-001
SHIFT
REGISTER
APPLICATIONS
DOCSIS 2.0 and Euro-DOCSIS cable modems
CATV set-top boxes
CATV telephony modems
Coaxial and twisted pair line drivers
GND
DATEN
DATA
CLK
TXEN
SLEEP
Figure 1. Functional Block Diagram
–40
GENERAL DESCRIPTION
The AD8324
1
is a low cost amplifier designed for coaxial line
driving. The features and specifications make the AD8324
ideally suited for DOCSIS 2.0 and Euro-DOCSIS applications.
The gain of the AD8324 is digitally controlled. An 8-bit serial
word determines the desired output gain over a 59 dB range,
resulting in gain changes of 1 dB/LSB.
The AD8324 accepts a differential or single-ended input signal.
The output is specified for driving a 75 Ω load through a 1:1
transformer.
Distortion performance of –54 dBc is achieved with an output
level up to 61 dBmV at 65 MHz bandwidth.
This device has a sleep mode function that reduces the quies-
cent current to 30 μA and a full power-down function that
reduces power-down current to 2.5 mA.
The AD8324 is packaged in a low cost 20-lead LFCSP package
and a 20-lead QSOP package. The AD8324 operates from a
single 3.3 V supply.
1
–50
V
OUT
= 61dBmV @ DEC 60
THIRD HARMONIC
DISTORTION (dBc)
–60
–70
V
OUT
= 61dBmV @ DEC 60
SECOND HARMONIC
04339-0-002
–80
5
15
25
35
45
FREQUENCY (MHz)
55
65
Figure 2. Worst Harmonic Distortion vs. Frequency
Patent pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD8324
TABLE OF CONTENTS
Specifications..................................................................................... 3
Logic Inputs (TTL/CMOS Compatible Logic)......................... 4
Timing Requirements .................................................................. 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Functional Descriptions ........................ 6
Typical Performance Characteristics ............................................. 7
Applications..................................................................................... 10
General Applications.................................................................. 10
Circuit Description..................................................................... 10
Gain Programming for the AD8324 ........................................ 10
Input Bias, Impedance, and Termination................................ 10
Output Bias, Impedance, and Termination............................. 10
Power Supply............................................................................... 11
Signal Integrity Layout Considerations ................................... 11
Initial Power-Up ......................................................................... 11
RAMP Pin and BYP Pin Features ............................................ 11
Power Saving Features ............................................................... 12
Distortion, Adjacent Channel Power, and DOCSIS .............. 12
Utilizing Diplex Filters............................................................... 12
Noise and DOCSIS..................................................................... 12
Evaluation Board Features and Operation.............................. 13
Differential Signal Source ......................................................... 13
Differential Signal from Single-Ended Source ....................... 13
Single-Ended Source.................................................................. 13
Overshoot on PC Printer Ports ................................................ 14
Installing Visual Basic Control Software................................. 14
Running AD8324 Software ....................................................... 14
Controlling Gain/Attenuation of the AD8324 ....................... 14
Transmit Enable and Sleep Mode............................................. 14
Memory Functions..................................................................... 14
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
7/05—Rev. 0 to Rev. A
Updated Absolute Maximum Ratings Page ...................................5
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
Revision 0: Initial Version
Rev. A | Page 2 of 16
AD8324
SPECIFICATIONS
T
A
= 25°C, V
CC
= 3.3 V, R
L
= R
IN
= 75 Ω, V
IN
(Differential) = 27.5 dBmV, unless otherwise noted. The AD8324 is characterized using a 1:1
transformer
1
at the device output.
Table 1.
Parameter
INPUT CHARACTERISTICS
Conditions
Output = 61 dBmV, Max Gain
Single-Ended Input
Differential Input
Min
Typ
27.5
550
1100
2
Max
Unit
dBmV
Ω
Ω
pF
Specified AC Voltage
Input Resistance
Input Capacitance
GAIN CONTROL INTERFACE
Voltage Gain Range
Max Gain
Min Gain
Output Step Size
2
Output Step Size Temperature Coefficient
OUTPUT CHARACTERISTICS
Gain Code = 60 Dec
Gain Code = 1 Dec
T
A
= –40°C to +85°C
All Gain Codes (1–60 Decimal Codes)
f = 65 MHz
Max Gain, f = 10 MHz, Output Referred
Min Gain, f = 10 MHz, Input Referred
f = 10 MHz
f = 10 MHz
f = 10 MHz
f = 10 MHz
TX Enable and TX Disable
58
32.5
–26.5
0.6
59.0
33.5
–25.5
1.0
±0.004
100
1.7
21
3.7
157
1.3
1.1
15.5
75 ± 30%
4
60
34.5
–24.5
1.4
dB
dB
dB
dB/LSB
dB/°C
MHz
dB
dBm
dBm
Bandwidth (–3 dB)
Bandwidth Roll-Off
1 dB Compression Point
3
Output Noise
2
Max Gain
Min Gain
Transmit Disable
Noise Figure
2
Max Gain
Differential Output Impedance
OVERALL PERFORMANCE
19.6
2.1
166
1.5
1.2
16.0
nV/√Hz
nV/√Hz
nV/√Hz
dB
Ω
Second-Order Harmonic Distortion
5, 3
f = 33 MHz, V
OUT
= 61 dBmV @ Max Gain
f = 65 MHz, V
OUT
= 61 dBmV @ Max Gain
f = 21 MHz, V
OUT
= 61 dBmV @ Max Gain
f = 65 MHz, V
OUT
= 61 dBmV @ Max Gain
Max Gain, f = 65 MHz
Max Gain, V
IN
= 0
Max Gain, V
IN
= 0
Equivalent Output = 31 dBmV
Equivalent Output = 61 dBmV
Min to Max Gain
Max Gain, V
IN
= 27.5 dBmV
3.13
195
25
1
–40
Third-Order Harmonic Distortion
5 , 3
ACPR
2, 6
Isolation (Transmit Disable)
2
POWER CONTROL
–66
–58
–59
–54
–61
–75
2.5
3.8
2.5
27
60
30
3.3
207
39
2.5
30
–60
–53
–57.5
–52.5
–58
–70
dBc
dBc
dBc
dBc
dBc
dB
μs
μs
mV p-p
mV p-p
ns
ns
TX Enable Settling Time
TX Disable Settling Time
Output Switching Transients
3
Output Settling
Due to Gain Change
Due to Input Step Change
POWER SUPPLY
6
71
Operating Range
Quiescent Current
Max Gain
Min Gain
Transmit Disable (TXEN = 0)
SLEEP Mode (Power-Down)
LFCSP
3.47
235
50
4
500
+85
V
mA
mA
mA
μA
°C
OPERATING TEMPERATURE RANGE
QSOP
1
2
–25
+70
°C
TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB @ 10 MHz.
Guaranteed by design and characterization to ±6 sigma for T
A
= 25°C.
3
Guaranteed by design and characterization to ±3 sigma for T
A
= 25°C.
4
Measured through a 1:1 transformer.
5
Specification is worst case over all gain codes.
6
V
IN
= 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
Rev. A | Page 3 of 16
AD8324
LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC)
DATEN, CLK, SDATA, TXEN, SLEEP, V
CC
= 3.3 V, unless otherwise noted.
Table 2.
Parameter
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current (V
INH
= 3.3 V), CLK, SDATA, DATEN
Logic 0 Current (V
INL
= 0 V), CLK, SDATA, DATEN
Logic 1 Current (V
INH
= 3.3 V), TXEN
Logic 0 Current (V
INL
= 0 V), TXEN
Logic 1 Current (V
INH
= 3.3 V), SLEEP
Logic 0 Current (V
INL
= 0 V), SLEEP
Min
2.1
0
0
−600
50
−250
50
−250
Typ
Max
3.3
0.8
20
−100
190
−30
190
−30
Unit
V
V
nA
nA
μA
μA
μA
μA
TIMING REQUIREMENTS
V
CC
= 3.3 V, t
R
= t
F
= 4 ns, f
CLK
= 8 MHz, unless otherwise noted.
Table 3.
Parameter
Clock Pulse Width (t
WH
)
Clock Period (t
C
)
Setup Time SDATA vs. Clock (t
DS
)
Setup Time DATEN vs. Clock (t
ES
)
Hold Time SDATA vs. Clock (t
DH
)
Hold Time DATEN vs. Clock (t
EH
)
Input Rise and Fall Times, SDATA, DATEN, Clock (t
R
, t
F
)
Min
16.0
32.0
5.0
15.0
5.0
3.0
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
10
t
DS
VALID DATA WORD G1
MSB . . . LSB
VALID DATA BIT
VALID DATA WORD G2
SDATA
t
C
t
VUH
SDATA
CLK
MSB
MSB-1
MSB-2
t
ES
t
EH
t
DS
DATEN
8 CLOCK CYCLES
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
t
DH
CLK
TXEN
t
OFF
t
GS
t
CN
04339-0-0030
Figure 4. SDATA Timng
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
Figure 3. Serial Interface Timing
Rev. A | Page 4 of 16
04339-0-004
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