V54C33332G2V-6 datasheet, PDF - EEWORLD Datasheet

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V54C33332G2V-6: DescriptionSynchronous DRAM, 1MX32, 5.4ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, TQFP-100; Categorystorage storage; File Size117KB，23 Pages; ManufacturerMosel Vitelic Corporation ( MVC ); Websitehttp://www.moselvitelic.com

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V54C33332G2V-6 Overview

Synchronous DRAM, 1MX32, 5.4ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, TQFP-100

V54C33332G2V-6 Parametric

Parameter Name	Attribute value
Maker	Mosel Vitelic Corporation ( MVC )
Parts packaging code	QFP
package instruction	TQFP,
Contacts	100
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PQFP-G100
length	20 mm
memory density	33554432 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	100
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX32
Package body material	PLASTIC/EPOXY
encapsulated code	TQFP
Package shape	RECTANGULAR
Package form	FLATPACK, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm

V54C33332G2V-6 Preview

MOSEL VITELIC

V54C33332G2V

166/143 MHz 3.3 VOLT

ULTRA HIGH PERFORMANCE

1M X 32 SDRAM 2 BANKS X 512Kbit X 32

PRELIMINARY

V54C33332G2V

Clock Frequency (t

)

Latency

Cycle Time (t

)

Access Time (t

)

-6

166

5.4

-7

143

5.4

-8

125

-10

100

Unit

MHz

clocks

Features

JEDEC Standard 3.3V Power Supply

The V54C33332G2V is ideally suited for high

performance graphics peripheral applications

Single Pulsed RAS Interface

Programmable CAS Latency: 2, 3

All Inputs are sampled at the positive going edge

of clock

Programmable Wrap Sequence: Sequential or

Interleave

Programmable Burst Length: 1, 2, 4, 8 and Full

Page for Sequential and 1, 2, 4, 8 for Interleave

DQM 0-3 for Byte Masking

Auto & Self Refresh

2K Refresh Cycles/32 ms

Burst Read with Single Write Operation

Description

The V54C33332G2V is a 33,554,432 bits syn-

chronous high data rate DRAM organized as 2 x

524,288 words by 32 bits. The device is designed to

comply with JEDEC standards set for synchronous

DRAM products, both electrically and mechanically.

Synchronous design allows precise cycle control

with the system clock. The CAS latency, burst

length and burst sequence must be programmed

into device prior to access operation.

V54C33332G2V Rev. 1.4 August 1999

MOSEL VITELIC

100 Pin TQFP

PIN CONFIGURATION

Top View

VDDQ

VSSQ

VDDQ

VSSQ

VDDQ

VDD

VSSQ

VDDQ

DQM

DQM1

CLK

CKE

V54C33332G2V

V54C33332G2V Rev. 1.4 August 1999

VDDQ

VSSQ

VDDQ

VSSQ

VDDQ

VDD

VSSQ

VDDQ

DQM

CAS

RAS

VSSQ

VDD

VSSQ

100

100 pin TQFP

20 x 14 mm

0.65 mm pitch

(Marking side)

VDD

V54C33332G2V-01

MOSEL VITELIC

Block Diagram

V54C33332G2V

Write

Control

Logic

DQMi

MUX

Input

Buffer

Column Decoder

DQMi

Memory Array

Bank 1

512k x 32

Output

Buffer

Column Decoder

Sense Amplifier

CLK

CKE

RAS

CAS

DQMi

Timing

Memory Array

Bank 0

512k x 32

Row

Decoder

Sense Amplifier

-DQ

Row

Decoder

Row Address

Buffer

Column Address

Counter

Latency &

Burst Length

CLK

Programming

-A

, BA

Column Address

Buffer

Row Addresses

Refresh

Counter

Address

-A

Column Addresses

V54C33332G2V-02

V54C33332G2V Rev. 1.4 August 1999

MOSEL VITELIC

Signal Pin Description

CLK

CKE

V54C33332G2V

Name

Clock Input

Clock Enable

Input Function

System clock input. Active on the positive rising edge to sample all inputs

Activates the CLK signal when high and deactivates the CLK when low.

CKE low initiates the power down mode, suspend mode, or the self re-

fresh mode

Disables or enables device operation by masking or enabling all inputs

except CLK, CKE and DQMi

Latches row addresses on the positive edge of CLK with RAS low. En-

ables row access & precharge

Latches column addresses on the positive edge of CLK with CAS low.

Enables column access

Enables write operation

During a bank activate command, A

-A

defines the row address.

During a read or write command, A

-A

defines the column address. In

addition to the column address A

is used to invoke auto precharge BA

define the bank to be precharged. A

is low, auto precharge is disabled

during a precharge cycle, If A

is high, both bank will be precharged, if

is low, the BA is used to decide which bank to precharge

Selects which bank to activate. BA low select bank A and high selects

bank B

Data inputs/output are multiplexed on the same pins

Makes data output Hi-Z. Blocks data input when DQM is active

Power Supply. +3.3V

0.3V/ground

Provides isolated power/ground to DQs for improved noise immunity

Chip Select

RAS

Row Address Strobe

CAS

Column Address Strobe

-A

Write Enable

Address

Bank Select

-DQ

DQMi

VDD/VSS

VDDQ/VSSQ

Data Input/Output

Data Input/Output Mask

Power Supply/Ground

Data Output Power/Ground

No Connection

V54C33332G2V Rev. 1.4 August 1999

MOSEL VITELIC

Address Input for Mode Set (Mode Register Operation)

A10 A9

V54C33332G2V

Address Bus (Ax)

Mode Register

Write Burst Length

Test

Mode

CAS Latency

Burst Length

Write Burst Length

Length

Burst

Single Bit

Test Mode

Mode

Mode Reg

Set

Burst Type

Type

Sequential

Interleave

CAS Latency

Latency

Reserve

Burst Length

Length

Sequential

Reserve

Full Page

Interleave

Reserve

Power On and Initialization

The default power on state of the mode register is

supplier specific and may be undefined. The

following power on and initialization sequence

guarantees the device is preconditioned to each

users specific needs. Like a conventional DRAM,

the Synchronous DRAM must be powered up and

initialized in a predefined manner. During power on,

all VCC and VCCQ pins must be built up

simultaneously to the specified voltage when the

input signals are held in the “NOP” state. The power

on voltage must not exceed VCC+0.3V on any of

the input pins or VCC supplies. The CLK signal

must be started at the same time. After power on,

an initial pause of 200

s is required followed by a

precharge of both banks using the precharge

command. To prevent data contention on the DQ

bus during power on, it is required that the DQM and

CKE pins be held high during the initial pause

period. Once all banks have been precharged, the

Mode Register Set Command must be issued to

initialize the Mode Register. A minimum of eight

Auto Refresh cycles (CBR) are also required.These

may be done before or after programming the Mode

unpredictable start-up modes.

V54C33332G2V Rev. 1.4 August 1999

Programming the Mode Register

The Mode register designates the operation

mode at the read or write cycle. This register is di-

vided into 4 fields. A Burst Length Field to set the

length of the burst, an Addressing Selection bit to

program the column access sequence in a burst cy-

cle (interleaved or sequential), a CAS

Latency

Field

to set the access time at clock cycle and a Opera-

tion mode field to differentiate between normal op-

eration (Burst read and burst Write) and a special

Burst Read and Single Write mode. The mode set

operation must be done before any activate com-

mand after the initial power up. Any content of the

mode register can be altered by re-executing the

mode set command. All banks must be in pre-

charged state and CKE must be high at least one

clock before the mode set operation. After the mode

quired. Low signals of RAS, CAS, and WE and DSF

at the positive edge of the clock activate the mode

set operation. Address input data at this timing

defines parameters to be set as shown in the previ-

ous table.

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V54C33332G2V-6 Related Products

	V54C33332G2V-6	V54C33332G2V-7	V54C33332G2V-8
Description	Synchronous DRAM, 1MX32, 5.4ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, TQFP-100	Synchronous DRAM, 1MX32, 5.4ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, TQFP-100	Synchronous DRAM, 1MX32, 6ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, TQFP-100
Maker	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )
Parts packaging code	QFP	QFP	QFP
package instruction	TQFP,	TQFP,	TQFP,
Contacts	100	100	100
Reach Compliance Code	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	5.4 ns	5.4 ns	6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
length	20 mm	20 mm	20 mm
memory density	33554432 bit	33554432 bit	33554432 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	32	32	32
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	100	100	100
word count	1048576 words	1048576 words	1048576 words
character code	1000000	1000000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C
organize	1MX32	1MX32	1MX32
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TQFP	TQFP	TQFP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, THIN PROFILE	FLATPACK, THIN PROFILE	FLATPACK, THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD
width	14 mm	14 mm	14 mm

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